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Multi-core Processor Scheduling with Respect to Data Bus Bandwidth
Communications in Computer and Information Science - Advances in Optimization and Applications
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10.1007/978-3-030-65739-0_5
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2020
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pp. 55-69
Author(s):
Anton V. Eremeev
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Anton A. Malakhov
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Maxim A. Sakhno
◽
Maria Y. Sosnovskaya
Keyword(s):
Processor Scheduling
◽
Data Bus
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Multi Core Processor
Download Full-text
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References
Multi-Core Processor Scheduling Algorithm under The Influence Of Process Variation
Proceedings of the 2018 2nd International Conference on Algorithms, Computing and Systems - ICACS '18
◽
10.1145/3242840.3242847
◽
2018
◽
Author(s):
Xiaohui Wei
◽
Lishuang Su
◽
Jingweijia Tan
Keyword(s):
Process Variation
◽
Scheduling Algorithm
◽
Processor Scheduling
◽
Multi Core Processor
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Proposal and Evaluation of Mutual Exclusion Method using Lock-free Algorism for Embedded Systems using Multi-core Processor
IEEJ Transactions on Electronics Information and Systems
◽
10.1541/ieejeiss.139.802
◽
2019
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Vol 139
(7)
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pp. 802-811
Author(s):
Kenta Fujimoto
◽
Shingo Oidate
◽
Yuhei Yabuta
◽
Atsuyuki Takahashi
◽
Takuya Yamasaki
◽
...
Keyword(s):
Embedded Systems
◽
Mutual Exclusion
◽
Exclusion Method
◽
Multi Core Processor
Download Full-text
Fiber optic distributed system data bus
International Congress on Applications of Lasers & Electro-Optics
◽
10.2351/1.5057349
◽
1982
◽
Author(s):
George E. Dailey
Keyword(s):
Distributed System
◽
Fiber Optic
◽
System Data
◽
Data Bus
Download Full-text
Hybrid Parallel FEM on PC Cluster with Multi-core Processor
2020 23rd International Conference on Electrical Machines and Systems (ICEMS)
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10.23919/icems50442.2020.9291171
◽
2020
◽
Author(s):
T. Yamaguchi
◽
Y. Kawase
◽
T. Murase
Keyword(s):
Pc Cluster
◽
Parallel Fem
◽
Multi Core Processor
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A new greedy algorithm for multi-processor scheduling with gang scheduling
i-manager’s Journal on Software Engineering
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10.26634/jse.5.1.1202
◽
2010
◽
Vol 5
(1)
◽
pp. 7-12
Author(s):
Sarath B. Siyambalapitiya
◽
M. Sandirigama
Keyword(s):
Greedy Algorithm
◽
Processor Scheduling
◽
Gang Scheduling
Download Full-text
Performance Analysis of Hamming Code for Fault Tolerant 8-bit data bus in VDSM technology
i-manager’s Journal on Software Engineering
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10.26634/jse.4.4.1180
◽
2010
◽
Vol 4
(4)
◽
pp. 55-60
Author(s):
Sathish A
◽
M. Chennakesavulu
◽
M. Madhavi Latha
◽
K. Lal Kishore
Keyword(s):
Performance Analysis
◽
Fault Tolerant
◽
Hamming Code
◽
Data Bus
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A Technique to Reduce Data-Bus Coupling Transitions in DSM Technology
i-manager’s Journal on Software Engineering
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10.26634/jse.4.2.1073
◽
2009
◽
Vol 4
(2)
◽
pp. 67-73
Author(s):
Sathish A
◽
M. Madhavi Latha
◽
K. Lal Kishore
◽
M.V. Subramanyam
◽
C.S. Reddy
Keyword(s):
Data Bus
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Specification for data transfer between agricultural tractors and attached machinery (data bus protocol)
10.3403/00730303u
◽
2015
◽
Keyword(s):
Data Transfer
◽
Data Bus
◽
Agricultural Tractors
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Aerospace series. In-line couplers for use in multiplex data bus systems in accordance with MIL-STD-1553B
10.3403/02450781u
◽
2015
◽
Keyword(s):
Data Bus
Download Full-text
Aerospace series. In-line couplers for use in multiplex data bus systems in accordance with MIL-STD-1553B
10.3403/02450778u
◽
2015
◽
Keyword(s):
Data Bus
Download Full-text
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