Analisis Performa pada Video Graphic Array (VGA) Nvidia GTX 950M DDR3 dan Nvidia GTX 950M GDDR5

Video Graphic Array card (VGA) berfungsi untuk memproses data grafik atau sinyal digital pada komputer lalu kemudian sinyal grafik tersebut ditransfer ke layar monitor. VGA card yang dipakai untuk benchmark adalah NVIDIA GTX 950M GDDR5 dan NVIDIA GTX 950M DDR3. VGA card ini cukup diminati karena harga yang terjangkau serta performa yang tinggi dimana kartu grafis ini sudah mempunyai lebar jalur data (bus width) sebesar 128 bit serta terdiri dari varian DDR3 dan GDDR5. Pengambilan data spesifikasi dan performa diambil dari situs Jagat Review Gatot Tri [9] dan Notebookcheck Otshoff [8] yang mana dari data tersebut akan dilakukan analisa terhadap hasil benchmark yang didapat. Berdasarkan data dari spesifikasi dan benchmarking VGA card yang diperoleh, diketahui bahwa perbedaan Double-Data-Rate (DDR) pada Video Random Access Memory (VRAM) berpengaruh besar pada proses merender dan menampilkan gambar. VGA card memiliki komponen-komponen yang saling bekerja sama secara sederhana yaitu chip GPU, besar VRAM, dan tipe DDR. Oleh karena itu, perbedaan tipe DDR pada sebuah VGA card merupakan hal penting dalam performansi sebuah kartu grafis.

Uma Proposta de Barramento de Dados para Integração de Serviços Públicos Digitais

O uso de tecnologias que visam desburocratizar serviços públicos são de suma importância por sociedades ao redor de todo o mundo. Com a utilização de artefatos e práticas tecnológicas, é possível economizar financeiramente e em tempo de trabalho. A interoperabilidade de dados e informações entre diferentes Sistemas de Informação em qualquer ecossistema moderno de tecnologia é um item necessário para consultas e validações em bases de dados distintas. Essa troca de dados em ambientes governamentais se faz necessária na entrega rápida e eficaz de serviços públicos digitais para a população. Este trabalho propõe a utilização de um barramento que auxilia a interoperabilidade visando um impulso tecnológico em Governos Eletrônicos. Tal proposta de barramento, chamado IO Data Bus, se mostrou promissor através de simulações práticas utilizando na prova de conceito o barramento de troca de dados X-Road, elemento esse que proporcionou a base tecnológica da Estônia Digital. Como embasamento no nosso experimento, utilizamos o exemplo do pagamento do Auxílio Emergencial no Brasil, durante o período de crise causada pela pandemia do novo coronavírus.

CPB High-Speed Optical Data Buses for Microprocessor Systems

Рассмотрены вопросы формирования оптического интерконнекта между СБИС на печатных платах с использованием фторсодержащих полимерных материалов. Обсуждаются различные аспекты технологии УФ-фотолитографии для создания полимерных волноводов. Приводятся результаты исследований, направленных на формирование высокоскоростной оптической шины передачи данных для микропроцессорных вычислительных систем (суперЭВМ) с использованием массивов полимерных волноводов на печатной плате. The study deals with the optical interconnect between VLSIs on a PCB with fluorine-containing polymers. Various aspects of the UF photolithography for making polymer waveguides are discussed. The results of the research aimed at making a highspeed optical data bus for SoC (supercomputers) with PCB polymer waveguide arrays.

Parallel entangling gate operations and two-way quantum communication in spin chains

The power of a quantum circuit is determined through the number of two-qubit entangling gates that can be performed within the coherence time of the system. In the absence of parallel quantum gate operations, this would make the quantum simulators limited to shallow circuits. Here, we propose a protocol to parallelize the implementation of two-qubit entangling gates between multiple users which are spatially separated, and use a commonly shared spin chain data-bus. Our protocol works through inducing effective interaction between each pair of qubits without disturbing the others, therefore, it increases the rate of gate operations without creating crosstalk. This is achieved by tuning the Hamiltonian parameters appropriately, described in the form of two different strategies. The tuning of the parameters makes different bilocalized eigenstates responsible for the realization of the entangling gates between different pairs of distant qubits. Remarkably, the performance of our protocol is robust against increasing the length of the data-bus and the number of users. Moreover, we show that this protocol can tolerate various types of disorders and is applicable in the context of superconductor-based systems. The proposed protocol can serve for realizing two-way quantum communication.

Design And Development Of Power And Attitude Control Subsystems For RYESAT

This thesis describes the design and development of Ryerson University's first CubeSat (RyeSat) with a focus on power and attitude control subsystems. This satellite is intended to become the initial of a series of CubeSats built by Ryerson University to perform research in spacecraft control algorithms and actuators. RyeSat is built around a standard interface, which specifies both a data-bus and a switchable power supply system for non critical systems. To facilitate the development of this satellite a prototype power subsystem was created, programmed and tested. In addition to developing the system's architecture and power subsystem; analysis was preformed to size both reaction wheels and magnetic torquers. This analysis showed that a commercially available motor could be adapted to fulfill the attitude control requirements of a CubeSat and also showed that miniature magnetic torque rods would be more efficient that magnetic torque coils typically used on CubeSats. Finally, control laws for these actuators were designed and an adaptive nonlinear sliding mode controller for reaction wheels was applied to control the 3-axis attitude motion of RyeSat.

Design And Development Of Power And Attitude Control Subsystems For RYESAT

This thesis describes the design and development of Ryerson University's first CubeSat (RyeSat) with a focus on power and attitude control subsystems. This satellite is intended to become the initial of a series of CubeSats built by Ryerson University to perform research in spacecraft control algorithms and actuators. RyeSat is built around a standard interface, which specifies both a data-bus and a switchable power supply system for non critical systems. To facilitate the development of this satellite a prototype power subsystem was created, programmed and tested. In addition to developing the system's architecture and power subsystem; analysis was preformed to size both reaction wheels and magnetic torquers. This analysis showed that a commercially available motor could be adapted to fulfill the attitude control requirements of a CubeSat and also showed that miniature magnetic torque rods would be more efficient that magnetic torque coils typically used on CubeSats. Finally, control laws for these actuators were designed and an adaptive nonlinear sliding mode controller for reaction wheels was applied to control the 3-axis attitude motion of RyeSat.

Addressing multiple bit/symbol errors in DRAM subsystem

As DRAM technology continues to evolve towards smaller feature sizes and increased densities, faults in DRAM subsystem are becoming more severe. Current servers mostly use CHIPKILL based schemes to tolerate up-to one/two symbol errors per DRAM beat. Such schemes may not detect multiple symbol errors arising due to faults in multiple devices and/or data-bus, address bus. In this article, we introduce Single Symbol Correction Multiple Symbol Detection (SSCMSD)—a novel error handling scheme to correct single-symbol errors and detect multi-symbol errors. Our scheme makes use of a hash in combination with Error Correcting Code (ECC) to avoid silent data corruptions (SDCs). We develop a novel scheme that deploys 32-bit CRC along with Reed-Solomon code to implement SSCMSD for a ×4 based DDR4 system. Simulation based experiments show that our scheme effectively guards against device, data-bus and address-bus errors only limited by the aliasing probability of the hash. Our novel design enabled us to achieve this without introducing additional READ latency. We need 19 chips per rank, 76 data bus-lines and additional hash-logic at the memory controller.