Balanced and Compressed Coordinate Layout for the Sparse Matrix-Vector Product on GPUs

Author(s):  
José Ignacio Aliaga ◽  
Hartwig Anzt ◽  
Enrique S. Quintana-Ortí ◽  
Andrés E. Tomás ◽  
Yuhsiang M. Tsai
Author(s):  
Jörg Bornschein

An FPGA-based coprocessor has been implemented which simulates the dynamics of a large recurrent neural network composed of binary neurons. The design has been used for unsupervised learning of receptive fields. Since the number of neurons to be simulated (>104) exceeds the available FPGA logic capacity for direct implementation, a set of streaming processors has been designed. Given the state- and activity vectors of the neurons at time t and a sparse connectivity matrix, these streaming processors calculate the state- and activity vectors for time t + 1. The operation implemented by the streaming processors can be understood as a generalized form of a sparse matrix vector product (SpMxV). The largest dataset, the sparse connectivity matrix, is stored and processed in a compressed format to better utilize the available memory bandwidth.


2011 ◽  
Vol 116 ◽  
pp. 49-63 ◽  
Author(s):  
Adam Dziekonski ◽  
Adam Lamecki ◽  
Michal Mrozowski

2012 ◽  
Vol 38 (8) ◽  
pp. 408-420 ◽  
Author(s):  
Francisco Vázquez ◽  
José Jesús Fernández ◽  
Ester M. Garzón

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