A Comparative Study of Speech Processing in Microphone Arrays with Multichannel Alignment and Zelinski Post-Filtering

Author(s):  
Sergei Aleinik ◽  
Mikhail Stolbov
1996 ◽  
Vol 100 (4) ◽  
pp. 2696-2696
Author(s):  
Michael W. Hoffman ◽  
Zhao Li

2004 ◽  
Vol 116 (4) ◽  
pp. 2498-2499 ◽  
Author(s):  
Gary W. Elko ◽  
George V. Frisk

2021 ◽  
Vol 16 ◽  
pp. 146-154
Author(s):  
Khamlich Salah Eddine ◽  
Khamlich Fathallah ◽  
Issam Atouf ◽  
Benrabh Mohamed

Speech processing in real time requires the use of fast, reconfigurable electronic circuits capable of handling large amounts of information generated by the audio source. This article presents hardware implementations of a multilayer perceptron (MLP) and the MFCC algorithm for speech recognition. These algorithms have been implemented in hardware and tested in an on-board electronic card based on a reconfigurable circuit (FPGA). We also present a comparative study between several architectures of MLP and with the literature on the level of costs with regard to the surface of silicon, the speed and the computing resources required. Following the FPGA circuit modification, we created NIOSII processors to physically implement the architecture of ANN-type MLPs and MFCC speech recognition algorithms and perform real-time speech recognition functions.


2020 ◽  
Author(s):  
Bruno Oliveira Ferreira de Souza ◽  
Éve‐Marie Frigon ◽  
Robert Tremblay‐Laliberté ◽  
Christian Casanova ◽  
Denis Boire

Sign in / Sign up

Export Citation Format

Share Document