Shared Cache Allocation Based on Fairness in a Chip Multiprocessor Architecture

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering - Advanced Hybrid Information Processing ◽

10.1007/978-3-319-73317-3_58 ◽

2018 ◽

pp. 501-504

Author(s):

Dongfang Wang ◽

Jingmei Li

Keyword(s):

Chip Multiprocessor ◽

Shared Cache ◽

Multiprocessor Architecture ◽

Cache Allocation

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Quality of service shared cache management in chip multiprocessor architecture

ACM Transactions on Architecture and Code Optimization ◽

10.1145/1880037.1880039 ◽

2010 ◽

Vol 7 (3) ◽

pp. 1-33 ◽

Author(s):

Fei Guo ◽

Yan Solihin ◽

Li Zhao ◽

Ravishankar Iyer

Keyword(s):

Quality Of Service ◽

Chip Multiprocessor ◽

Cache Management ◽

Shared Cache ◽

Multiprocessor Architecture

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Avoiding common scalability pitfalls in shared-cache chip multiprocessor design

2019 International Conference on Engineering and Telecommunication (EnT) ◽

10.1109/ent47717.2019.9030579 ◽

2019 ◽

Author(s):

Yuri A. Nedbailo

Keyword(s):

Chip Multiprocessor ◽

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Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture

Languages and Compilers for Parallel Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-540-85261-2_18 ◽

2008 ◽

pp. 261-275

Author(s):

Slo-Li Chu

Keyword(s):

Block Scheduling ◽

Chip Multiprocessor ◽

Multiprocessor Architecture

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P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

Wireless Personal Communications ◽

10.1007/s11277-020-07529-2 ◽

2020 ◽

Vol 114 (4) ◽

pp. 3295-3319

Author(s):

Khyamling Parane ◽

B. M. Prabhu Prasad ◽

Basavaraj Talawar

Keyword(s):

Performance Evaluation ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Chip Multiprocessor ◽

Multiprocessor Architecture

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A novel 3D crossbar-based chip multiprocessor architecture

2013 Second International Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC) ◽

10.1109/jec-ecc.2013.6766390 ◽

2013 ◽

Author(s):

Mostafa Mahmoud ◽

Amr Wassal

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture

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An on-chip multiprocessor architecture with a non-blocking synchronization mechanism

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium ◽

10.1109/eurmic.1999.794505 ◽

1999 ◽

Author(s):

R. Kobayashi ◽

M. Iwata ◽

Y. Ogawa ◽

H. Ando ◽

T. Shimada

Keyword(s):

Chip Multiprocessor ◽

Synchronization Mechanism ◽

Multiprocessor Architecture ◽

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A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity

2007 IEEE International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2007.370528 ◽

2007 ◽

Author(s):

Engin Ipek ◽

Meyrem Kirman ◽

Nevin Kirman ◽

Jose F. Martinez

Keyword(s):

Chip Multiprocessor ◽

Software Diversity ◽

Multiprocessor Architecture

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Fair cache sharing and partitioning in a chip multiprocessor architecture

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004. ◽

10.1109/pact.2004.1342546 ◽

2004 ◽

Author(s):

Seongbeom Kim ◽

D. Chandra ◽

Yan Solihin

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture

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Chip size and performance evaluations of shared cache for on-chip multiprocessor

Systems and Computers in Japan ◽

10.1002/scj.20244 ◽

2005 ◽

Vol 36 (9) ◽

pp. 1-13

Author(s):

Takahiro Sasaki ◽

Tomohiro Inoue ◽

Nobuhiko Omori ◽

Tetsuo Hironaka ◽

Hans J. Mattausch ◽

...

Keyword(s):

Performance Evaluations ◽

Chip Multiprocessor ◽

Shared Cache ◽

Chip Size ◽

And Performance ◽

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A complete strategy for testing an on-chip multiprocessor architecture

IEEE Design & Test of Computers ◽

10.1109/54.980050 ◽

2002 ◽

Vol 19 (1) ◽

pp. 18-28 ◽

Author(s):

C. Aktouf

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture ◽

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