Joint Analysis and Reliability Test of Epoxy-Based Nano Silver Paste Under Different Pressure-Less Sintering Processes

Recent years, the sintered silver paste was introduced and further developed for power electronics packaging due to low processing temperature and high working temperature. The pressure-less sintering technology reduces the stress damage caused by the pressure to the chip, improves reliability, and is widely applied in manufacturing. Currently, most existed studies are focused on alcohol-based sintered silver pastes while resins have been demonstrated to improve the bonding properties of solder joints. Hence, the performance and sintering mechanisms with epoxy-based silver paste need to be further explored. In this work, a methodology for multi-factor investigation is settled on the epoxy-based silver paste to reveal the relationship between the strength and the different influence factors. We firstly analyzed the characteristics of commercialized epoxy-based silver paste samples, including silver content, silver particle size, organic paste composition, sample viscosity, and thermal conductivity. Samples were then prepared for shear tests and microstructure analysis under different pressure-less sintering temperatures, holding time, substrate surface, and chip size. Full factor analysis results were further discussed in detail for correlation. The influence factors were ranked from strong to weak as follows: sintering temperature, substrate surface, chip size, and holding time. Finally, a thermal cycling test was carried out for reliability analysis. Epoxy residues are one of the possible reasons which result in shear strength decreasing exponentially.

Scalable and compact photonic neural chip with low learning-capability-loss

Photonic computation has garnered huge attention due to its great potential to accelerate artificial neural network tasks at much higher clock rate to digital electronic alternatives. Especially, reconfigurable photonic processor consisting of Mach–Zehnder interferometer (MZI) mesh is promising for photonic matrix multiplier. It is desired to implement high-radix MZI mesh to boost the computation capability. Conventionally, three cascaded MZI meshes (two universal N × N unitary MZI mesh and one diagonal MZI mesh) are needed to express N × N weight matrix with O(N 2) MZIs requirements, which limits scalability seriously. Here, we propose a photonic matrix architecture using the real-part of one nonuniversal N × N unitary MZI mesh to represent the real-value matrix. In the applications like photonic neural network, it probable reduces the required MZIs to O(Nlog2 N) level while pay low cost on learning capability loss. Experimentally, we implement a 4 × 4 photonic neural chip and benchmark its performance in convolutional neural network for handwriting recognition task. Low learning-capability-loss is observed in our 4 × 4 chip compared to its counterpart based on conventional architecture using O(N 2) MZIs. While regarding the optical loss, chip size, power consumption, encoding error, our architecture exhibits all-round superiority.

Pressure Sensor with Novel Electrical Circuit Utilizing Bipolar Junction Transistor

<p>High sensitivity MEMS pressure sensor chip for different ranges (1 to 60 kPa) utilizing the novel electrical circuit of piezosensitive differential amplifier with negative feedback loop (PDA-NFL) is developed. Pressure sensor chip PDA-NFL utilizes two bipolar-junction transistors (BJT) with vertical n-p-n type structure (V-NPN) and eight piezoresistors (p-type). Both theoretical model of sensor response to pressure and temperature and experimental data are presented. Data confirms the applicability of theoretical model. Introduction of the amplifier allows for decreasing chip size while keeping the same sensitivity as a chip with classic Wheatstone bridge circuit.</p>

Pressure Sensor with New Electrical Circuit Utilizing Bipolar Junction Transistor

High sensitivity MEMS pressure sensor chip for different ranges (1 to 60 kPa) utilizing the novel electrical circuit of piezosensitive differential amplifier with negative feedback loop (PDA-NFL) is developed. Pressure sensor chip PDA-NFL utilizes two bipolar-junction transistors (BJT) with vertical n-p-n type structure (V-NPN) and eight piezoresistors (p–type). Both theoretical model of sensor response to pressure and temperature and experimental data are presented. Data confirms the applicability of theoretical model. Introduction of the amplifier allows for decreasing chip size while keeping the same sensitivity as a chip with classic Wheatstone bridge circuit.

Pressure Sensor with Novel Electrical Circuit Utilizing Bipolar Junction Transistor

<p>High sensitivity MEMS pressure sensor chip for different ranges (1 to 60 kPa) utilizing the novel electrical circuit of piezosensitive differential amplifier with negative feedback loop (PDA-NFL) is developed. Pressure sensor chip PDA-NFL utilizes two bipolar-junction transistors (BJT) with vertical n-p-n type structure (V-NPN) and eight piezoresistors (p-type). Both theoretical model of sensor response to pressure and temperature and experimental data are presented. Data confirms the applicability of theoretical model. Introduction of the amplifier allows for decreasing chip size while keeping the same sensitivity as a chip with classic Wheatstone bridge circuit.</p>

Pressure Sensor with New Electrical Circuit Utilizing Bipolar Junction Transistor

High sensitivity MEMS pressure sensor chip for different ranges (1 to 60 kPa) utilizing the novel electrical circuit of piezosensitive differential amplifier with negative feedback loop (PDA-NFL) is developed. Pressure sensor chip PDA-NFL utilizes two bipolar-junction transistors (BJT) with vertical n-p-n type structure (V-NPN) and eight piezoresistors (p-type). Both theoretical model of sensor response to pressure and temperature and experimental data are presented. Data confirms the applicability of theoretical model. Introduction of the amplifier allows for decreasing chip size while keeping the same sensitivity as a chip with classic Wheatstone bridge circuit.

On the mechanism of carrier recombination in downsized blue micro-LEDs

The mechanism of carrier recombination in downsized μ-LED chips from 100 × 100 to 10 × 10 μm2 on emission performance was systemically investigated. All photolithography processes for defining the μ-LED pattern were achieved by using a laser direct writing technique. This maskless technology achieved the glass-mask-free process, which not only can improve the exposure accuracy but also save the development time. The multi-functional SiO2 film as a passivation layer successfully reduced the leakage current density of μ-LED chips compared with the μ-LED chips without passivation layer. As decreasing the chip size to 10 × 10 μm2, the smallest chip size exhibited the highest ideality factor, which indicated the main carrier recombination at the high-defect-density zone in μ-LED chip leading to the decreased emission performance. The blue-shift phenomenon in the electroluminescence spectrum with decreasing the μ-LED chip size was due to the carrier screening effect and the band filling effect. The 10 × 10 μm2 μ-LED chip exhibited high EQE values in the high current density region with a less efficiency droop, and the max-EQE value was 18.8%. The luminance of 96 × 48 μ-LED array with the chip size of 20 × 20 μm2 exhibited a high value of 516 nits at the voltage of 3 V.

Processing Techniques with Heating Conditions for Multiferroic Systems of BiFeO3, BaTiO3, PbTiO3, CaTiO3 Thin Films

In this chapter, we have report a list of synthesis methods (including both synthesis steps & heating conditions) used for thin film fabrication of perovskite ABO3 (BiFeO3, BaTiO3, PbTiO3 and CaTiO3) based multiferroics (in both single-phase and composite materials). The processing of high quality multiferroic thin film have some features like epitaxial strain, physical phenomenon at atomic-level, interfacial coupling parameters to enhance device performance. Since these multiferroic thin films have ME properties such as electrical (dielectric, magnetoelectric coefficient & MC) and magnetic (ferromagnetic, magnetic susceptibility etc.) are heat sensitive, i.e. ME response at low as well as higher temperature might to enhance the device performance respect with long range ordering. The magnetoelectric coupling between ferromagnetism and ferroelectricity in multiferroic becomes suitable in the application of spintronics, memory and logic devices, and microelectronic memory or piezoelectric devices. In comparison with bulk multiferroic, the fabrication of multiferroic thin film with different structural geometries on substrate has reducible clamping effect. A brief procedure for multiferroic thin film fabrication in terms of their thermal conditions (temperature for film processing and annealing for crystallization) are described. Each synthesis methods have its own characteristic phenomenon in terms of film thickness, defects formation, crack free film, density, chip size, easier steps and availability etc. been described. A brief study towards phase structure and ME coupling for each multiferroic system of BiFeO3, BaTiO3, PbTiO3 and CaTiO3 is shown.

Research and Design of X-band Low Noise Amplifier Based on CMOS Process

Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).