The Reduced Address Space (RAS) for Application Memory Authentication

2008 ◽  
pp. 47-63 ◽  
Author(s):  
David Champagne ◽  
Reouven Elbaz ◽  
Ruby B. Lee
Keyword(s):  
Address Space

scholarly journals FAST PARALLEL PERMUTATION ALGORITHMS

1995 ◽  
Vol 05 (02) ◽  
pp. 139-148 ◽  
Author(s):  
TORBEN HAGERUP ◽  
JÖRG KELLER
Keyword(s):  
Simple Algorithm ◽  
Address Space ◽  
Erew Pram ◽  
Run Time ◽  
Local Storage ◽  
Improved Algorithm

We investigate the problem of permuting n data items on an EREW PRAM with p processors using little additional storage. We present a simple algorithm with run time O((n/p) log n) and an improved algorithm with run time O(n/p + log n log log (n/p)). Both algorithms require n additional global bits and O(1) local storage per processor. If prefix summation is supported at the instruction level, the run time of the improved algorithm is O(n/p). The algorithms can be used to rehash the address space of a PRAM emulation.

D-buffer: irregular image data storage made practical

2013 ◽  
Vol 21 (1) ◽  
Author(s):  
J. Lipowski
Keyword(s):  
Data Storage ◽  
Image Data ◽  
Development Aid ◽  
Graphics Hardware ◽  
Address Space ◽  
Output Data ◽  
Frame Buffer ◽  
New Methods ◽  
Hardware Architectures ◽  
Depth Buffer

AbstractModern hardware accelerated graphics pipelines are designed to operate on data in a so called streaming model. To process the data in this model one needs to impose some restrictions on input and output argument’s (most frequently represented by a two-dimensional frame buffer) memory structure. The output data regularity is obvious when we consider rasterizing hardware architecture, which draws 3D polygons using depth buffer to resolve the visible surface problem. But recently the user’s needs surpass those restrictions with increasing frequency. In this work we formulate and present new methods of irregular frame buffer storage and ordering. The so called deque buffer (or D-buffer) allows us to decrease the amount of memory used for storage as well as the memory latency cost by using pixel data ordering. Our findings are confirmed by experimental results that measure the processing time, which is up to four times shorter, when compared with previous work by other authors. We also include a detailed description of algorithms used for D-buffer construction on the last three consumer-grade graphics hardware architectures, as a guide for other researchers and a development aid for practitioners. The only theoretical requirement imposed by our method is the use of memory model with linear address space.

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