Language Model Using Neural Turing Machine Based on Localized Content-Based Addressing

The performance of a long short-term memory (LSTM) recurrent neural network (RNN)-based language model has been improved on language model benchmarks. Although a recurrent layer has been widely used, previous studies showed that an LSTM RNN-based language model (LM) cannot overcome the limitation of the context length. To train LMs on longer sequences, attention mechanism-based models have recently been used. In this paper, we propose a LM using a neural Turing machine (NTM) architecture based on localized content-based addressing (LCA). The NTM architecture is one of the attention-based model. However, the NTM encounters a problem with content-based addressing because all memory addresses need to be accessed for calculating cosine similarities. To address this problem, we propose an LCA method. The LCA method searches for the maximum of all cosine similarities generated from all memory addresses. Next, a specific memory area including the selected memory address is normalized with the softmax function. The LCA method is applied to pre-trained NTM-based LM during the test stage. The proposed architecture is evaluated on Penn Treebank and enwik8 LM tasks. The experimental results indicate that the proposed approach outperforms the previous NTM architecture.

Evolution of application-specific cache mappings

Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications for better run-times and energy consumptions. While one may adapt structural cache parameters such as cache and block sizes, we adapt the memory-address-to-cache-index mapping function to the needs of an application. Using a LEON3 embedded multi-core processor with reconfigurable cache mappings, a metaheuristic search procedure, and MiBench applications, we show in this work how to accurately compare non-deterministic performances of applications and how to use this information to implement an optimization procedure that evolves application-specific cache mappings for the LEON3 multi-core processor.

Secure Data Performance Analysis with OLSR and AODV Routing Protocols in MANET

MANETs are vigorous network to obligate node links due to the wireless frequency affect the network performance. It evaluates the link constancy by redefining the link availability that connected throughout a specific time period. MANETs have an identical status to acquaintance by the node resources with any other network. In this work, network is able to deal with vital reform that competent, consistent, and accessible network to perform enhance network protocol along with data security. AODV network nodes need connections broadcast forward the message that requested a connection that create a series of impermanent routes back to the requesting node. In this work, a link state protocol is calculated an alternative and fragmented path from source to destination by re-routing traffic through it, regardless of the locations of failure and the number of failed links. Also, the purpose of this research work is to provide secure bit data networking and occupy bit-memory address to enhance the node data capacity size, hence it reduces packets loss, delay time, and improve throughput when re-join the nodes while failure. OLSR generate a control overhead to maintain routing table to consume data traffic bandwidth. This study reduces the control overhead to improve the performance of OLSR by optimizing control messages intervals to have enhanced and secure data transmission. In this work, a secure and reliable bitdata is presented which have a memory address search process between two data address as simulated in this work.

CNN-Based Fault Localization Method Using Memory-Updated Patterns for Integration Test in an HiL Environment

Automotive electronic components are tested via hardware-in-the-loop (HiL) testing at the unit and integration test stages, according to ISO 26262. It is difficult to obtain debugging information from the HiL test because the simulator runs a black-box test automatically, depending on the scenario in the test script. At this time, debugging information can be obtained in HiL tests, using memory-updated information, without the source code or the debugging tool. However, this method does not know when the fault occurred, and it is difficult to select the starting point of debugging if the execution flow of the software is not known. In this paper, we propose a fault-localization method using a pattern in which each memory address is updated in the HiL test. Via a sequential pattern-mining algorithm in the memory-updated information of the transferred unit tests, memory-updated patterns are extracted, and the system learns using a convolutional neural network. Applying the learned pattern in the memory-updated information of the integration test can determine the fault point from the normal pattern. The point of departure from the normal pattern is highlighted as a fault-occurrence time, and updated addresses are presented as fault candidates. We applied the proposed method to an HiL test of an OSEK/VDX-based electronic control unit. Through fault-injection testing, we could find the cause of faults by checking the average memory address of 3.28%, and we could present the point of fault occurrence with an average accuracy of 80%.

Improve performance of the digital sinusoidal generator in FPGA by memory usage optimization

<p>This paper presented the improvement in the performance of the digital sinusoidal signal generator, which was implemented in FPGA, by optimizing the usage of the available memory onboard. The sine wave was generated by using a Lookup Table method, where its pre-calculated values were stored in the onboard memory, and its frequency can be adjustable by changing the incremental step value of the memory address. In this proposed research, the memory stores only 25000 samples of the first quarter from a period of a sine wave and thus, the output signal accuracy was increased and the output frequency range was expanded, compared to the previous research. The proposed design was successfully developed and implemented in ALTERA Cyclone III DE0 FPGA Development Board, and its functionality was validated via functional simulation in Modelsim and also hardware experimental results observation in SignalTap II.</p>