GDH Key Exchange Protocol for Group Security Among Hypercube Deployed IoT Devices

Author(s):  
Vimal Gaur ◽  
Rajneesh Kumar
Author(s):  
Luis Adrián Lizama-Pérez ◽  
José Mauricio López Romero

We introduce a novel key exchange protocol based on non-commutative matrix multiplication defined in $\mathbb{Z}_p^{n \times n}$. The security of our method does not rely on computational problems as integer factorization or discrete logarithm whose difficulty is conjectured. We claim that the unique eavesdropper's opportunity to get the secret/private key is by means of an exhaustive search which is equivalent to the unsorted database search problem. Furthermore, we show that the secret/private keys become indistinguishable to the eavesdropper. Remarkably, to achieve a 512-bit security level, the keys (public/private) are of the same size when matrix multiplication is done over a reduced 8-bit size modulo. Also, we discuss how to achieve key certification and Perfect Forward Secrecy (PFS). Therefore, Lizama's algorithm becomes a promising candidate to establish shared keys and secret communication between (IoT) devices in the quantum era.


The General Data Protection Regulation (GDPR) which was enforced in May 2018 clearly stated that the protection of data by organizations is a mandatory task. Protecting or securing data on data collecting and sensing devices used in the Internet-of-Things (IoT) platform is a challenge for the fact that the devices are resource-constrained in terms of operation frequency, hardware area, computational complexity, and power consumption. The first step to securing data on low-cost IoT devices is to generate keys for subsequent encryption and authentication. This paper, therefore, proposes and implements a lightweight key exchange protocol with the capability of authenticating the generated key without the need for public-key cryptography. The protocol is meant to be simple and make use of minimal hardware resources. It uses components such as the pseudorandom number and bit generators, dot product, XOR gates, shift registers and basic logic gates making it very resource-efficient. The hardware architecture of the protocol was implemented using Verilog Hardware Description Language (HDL) and synthesized using Xilinx ISE 14.7 software which includes XPower Analyzer for power estimation. The protocol was tested on a Field Programmable Gate Array (FPGA) board with a synthesizable Reduced Instruction Set Computer Five (RISC-V) processor core. The synthesis and simulation results which include area, maximum frequency, latency, and power consumption show that the protocol is suitable for IoT low-cost devices as compared to standard public-key primitives.


2006 ◽  
Vol 1 (2) ◽  
pp. 52-70
Author(s):  
Mohammed A. Tawfiq ◽  
◽  
Sufyan T. Faraj Al-janabi ◽  
Abdul-Karim A. R. Kadhim ◽  
◽  
...  

2010 ◽  
Vol 30 (7) ◽  
pp. 1805-1808
Author(s):  
Shao-feng DENG ◽  
Fan DENG ◽  
Yi-fa LI

2020 ◽  
Vol 9 (12) ◽  
pp. 11169-11177
Author(s):  
A. J. Meshram ◽  
C. Meshram ◽  
S. D. Bagde ◽  
R. R. Meshram

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