Design of Carry Select Adder using BEC and Common Boolean Logic

Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.

An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wireless receivers

<p>Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.</p>

Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

Experimental Study on the Crushing Properties of Corn Stalks in Square Bales

With the development of straw baling mechanization technology, straw is stored in the form of square baling or round baling. At present, hammer mill or the guilt-cutting and rubbing combined mill is widely used to crush square bales of straw. These two kinds of crushing equipment have disadvantages such as low productivity, large power consumption, and poor crushing effect. This paper aims to study and analyze the crushing characteristics of square baled straw after unbaling, and lay a theoretical foundation for the later research and development of a special square baled straw crusher with high productivity, low power consumption, good crushing effect, and the simulation of the square baled corn straw crushing process. For this purpose, this study carried out a corn bale crushing experiment on the Instron 8801 fatigue test machine, and studied the effects of blade angle, water content and loading speed on corn bale crushing force through the response surface method. Test results showed that the crushing process includes the compression stage and shearing stage; in terms of single factor effect, with the increase in water content and blade angle, the crushing force of the corn bale increased, but the loading speed had no significant effect on the crushing force of the corn bale. In terms of interaction effect, there was interaction effect between moisture content and blade inclination angle, when moisture content was 10%, with the increase in blade inclination angle, the incremental speed of the crushing force also increased gradually. When the blade inclination angle was 10°, with the increase in moisture content, the incremental speed of the crushing force also increased, and the interaction effect of them jointly acted on the crushing force of the corn bales.

Experimental analysis of influence of double-layer bump foils on aerodynamic thrust foil bearings performance

Purpose Gas thrust foil bearings (GTFBs) are used to balance the axial load of engines. However, in some working conditions of large axial force, such as the use of single impeller air compressor, the load capacity of GTFBs is still insufficient. To solve this problem, the load capacity can be improved by increasing the stiffness of bump foil. The purpose of this paper is to explore a scheme to effectively improve the performance of thrust foil bearings. In the paper, the stiffness of bump foil is improved by increasing the thickness of bump foil and using double-layer bump foil. Design/methodology/approach The foil deformation of GTFBs supported by three different types of bump foils, the relationship between friction power consumption and external force and the difference of limited load capacity were measured by experimental method. Findings The variation of the foil deformation, bearing stiffness, friction power consumption with the external force at different speeds and limited load capacity are obtained. Based on experimental results, the selection scheme of bump foil thickness is obtained. Originality/value This paper provides a feasible method for the performance optimization of GTFBs.

A customizable, low-power, wireless, embedded sensing platform for resistive nanoscale sensors

Customizable, portable, battery-operated, wireless platforms for interfacing high-sensitivity nanoscale sensors are a means to improve spatiotemporal measurement coverage of physical parameters. Such a platform can enable the expansion of IoT for environmental and lifestyle applications. Here we report a platform capable of acquiring currents ranging from 1.5 nA to 7.2 µA full-scale with 20-bit resolution and variable sampling rates of up to 3.125 kSPS. In addition, it features a bipolar voltage programmable in the range of −10 V to +5 V with a 3.65 mV resolution. A Finite State Machine steers the system by executing a set of embedded functions. The FSM allows for dynamic, customized adjustments of the nanosensor bias, including elevated bias schemes for self-heating, measurement range, bandwidth, sampling rate, and measurement time intervals. Furthermore, it enables data logging on external memory (SD card) and data transmission over a Bluetooth low energy connection. The average power consumption of the platform is 64.5 mW for a measurement protocol of three samples per second, including a BLE advertisement of a 0 dBm transmission power. A state-of-the-art (SoA) application of the platform performance using a CNT nanosensor, exposed to NO2 gas concentrations from 200 ppb down to 1 ppb, has been demonstrated. Although sensor signals are measured for NO2 concentrations of 1 ppb, the 3σ limit of detection (LOD) of 23 ppb is determined (1σ: 7 ppb) in slope detection mode, including the sensor signal variations in repeated measurements. The platform’s wide current range and high versatility make it suitable for signal acquisition from resistive nanosensors such as silicon nanowires, carbon nanotubes, graphene, and other 2D materials. Along with its overall low power consumption, the proposed platform is highly suitable for various sensing applications within the context of IoT.

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

Agitation of Complex Fluids in Cylindrical Vessels by Newly Designed Anchor Impellers

The fluid flows and power consumption in a vessel stirred by anchor impellers are investigated in this paper. The case of rheologically complex fluids modeled by the Bingham-Papanastasiou model is considered. New modifications in the design of the classical anchor impeller are introduced. A horizontal blade is added to the standard geometry of the anchor, and the effect of its inclination angle (α) is explored. Four geometrical configurations are realized, namely: α = 0°, 20°, 40°, and 60°. The effects of the number of added horizontal blades, Reynolds number, and Bingham number are also examined. The obtained findings reveal that the most efficient impeller design is that with (case 4) arm blades inclined by 60°.This case allowed the most expansive cavern size with enhanced shearing in the whole vessel volume. The effect of adding second horizontal arm blades (with 60°) gave better hydrodynamic performance only with a slight increase in power consumption. A significant impact of Bingham number (Bn) was observed, where Bn = 5 allowed obtaining the lowest power input and most expansive well-stirred region.

2022 roadmap on neuromorphic computing and engineering

Modern computation based on the von Neumann architecture is today a mature cutting-edge science. In the Von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 1018 calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this Roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The Roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this Roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community.