DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

A Design Method for Low-cost and SOPC-based Flexible Lifting Control System

To efficiently reduce the development and production costs of the intelligent lifting control system, we introduce a design method for the intelligent lifting system with client-server architecture. We replace DSP processor core or DSP (Digital Signal processor) core with Nois II soft-core processor so that the design and production costs can be effectively cut. By replacing DSP processor or DSP processor core with Nois II soft-core processor, the design and production costs can be significantly reduced. In our design, loop vector control units work as a server processor, and a central computing unit with four independent multipliers and two adders is employed, with the implementation method based on a state machine. The experimental results prove effective in reducing resource requirements for FPGA (Field Programmable Gate Array), show that the proposed method can be successfully applied to the implementation of a complete intelligent flexible lifting control system on a low-end Altera Cyclone FPGA, and servo motor control achieves better dynamic performance

Power and Performance Evaluation of Memory-Intensive Applications

In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation.

Streaming video processing of marine scenes using advanced processor instructions

Современные полупроводниковые технологии позволяют перейти к более развитым системам видеонаблюдения, где преобразование и обработка видеоинформации выполняются непосредственно на этапе съемки и формирования видеопотока. Умные камеры расширяют функциональность встроенных видеосенсоров, обеспечивая параллельную высокоуровневую обработку видео. В предлагаемом исследовании проведена разработка адаптивных алгоритмов спектрального преобразования изображений морских сюжетов, позволяющие решить необходимые задачи в реальном времени.Актуальным становится решение задачи использования современных процессорных технологий с использованием последних достижений в архитектуре процессорного ядра, в частности расширенные SSE-инструкции. Рассмотрен математический аппарат реализации адаптивных алгоритмов дискретного косинусного преобразования на базе SSEархитектуры процессорного ядра. Предложенные алгоритмы динамически выполняют предварительный анализ движения и определяют оптимальные размеры видеокубов. Для оценки эффективности предложенных алгоритмов сжатия было использовано множество различных изображений морских судов, полученных с камер и расположенных на беспилотниках с высоты 100-400м. Показаны результаты моделирования предложенных алгоритмов обработки видеоинформации морских сюжетов и определены количественные оценки информационных показателей качества видеосистем кодирования и декодирования изображений. Modern semiconductor technologies allow us to move to more advanced video surveillance systems, where the transformation and processing of video information is performed directly at the stage of shooting and forming a video stream. Smart cameras even extend the functionality of the built-in video sensors, providing parallel high-level video processing. In the proposed study, adaptive algorithms for spectral transformation of images of marine plots were developed, which allow solving the necessary problems in real time. The solution of the problem of using modern processor technologies using the latest achievements in the architecture of the processor core, in particular, advanced SSE instructions, becomes relevant. The mathematical apparatus for implementing adaptive algorithms for discrete cosine transformation based on the SSE architecture of the processor core is considered. Proposed algorithms dynamically perform preliminary motion analysis and determine optimal dimensions of video cubes. To evaluate the effectiveness of the proposed compression algorithms, many different images of naval vessels obtained from cameras and located on drones from a height of 100-400m were used. The results of modeling the proposed algorithms for processing video information of marine scenes are shown and quantitative estimates of information quality indicators of video systems for encoding and decoding images are determined.

High Priority Arbitration for Less Burst Data Transactions for Improved Average Waiting Time of Multi-Processor Cores

The multi-processor cores in SoC which have high burst data transactions can play a critical role while accessing the shared resources such as the off-chip memory. These processor cores can starve other processor cores that have less burst data transactions while accessing the same shared resources. The starving issue of other processor cores leads to degrade the entire system performance of the SoC. However, the arbiter architecture in the SoC design plays the best solution to manage different processor core requests and granting one of them to access the shared resources according to different scheduling algorithms. In this paper, we have designed AXI interconnect, which includes arbiter architecture to connect four processor cores represented by the AXI masters and the off-chip memory represented by the salve. Each processor core (AXI Master) uses the AXI4 interface protocol to improve the system performance and the arbiter based on the static fixed-priority algorithm to improve the average waiting time for all the processor cores. The SoC design architecture is modeled in System Verilog HDL; simulation and synthesis are done by using the Vivado tool and FPGA ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1).

PROGRAMMING METHOD OF THE MDR32F9Q2I MICROCONTROLLER IN CONTROL AND MONITORING TASKS

Разработана методика, обеспечивающая полный спектр организации работ по программированию микроконтроллера MDR32F9Q2I, которая позволяет получить, в частности, системы управления и мониторинга источников вторичного электроснабжения. Программирование микроконтроллера, построенного на базе высокопроизводительного процессорного RISC ядра ARM, производилось в интегрированной среде разработки Eclipse IDE в операционной системе Windows 10 Pro. Интегрированная среда разработки Eclipse выбрана как наиболее удобная и доступная среда, поддерживает всевозможные типы языков программирования и непрерывную компиляцию. В настоящее время 16- и 32-битные микроконтроллеры быстро набирают популярность в сфере промышленных задач. Их применение обусловлено постоянно возрастающей сложностью задач, жесткими требованиями к производительности интегрируемых контроллеров управления, необходимостью иметь в электронных устройствах развитые органы пользовательского управления. Представленный стенд для моделирования, использующий интерфейсный мост между шинами I2C и 1-Wire - DS2482-100, преобразует протоколы между управляющим I2C микроконтроллером (мастером) и ведомыми 1-Wire устройствами, а также контролирует скорости нарастания и уменьшения напряжения в линии. Основой для написания класса DS2482 являются заголовочные файлы Arduino.h и OneWire.h, которые находятся в свободном доступе In this article, we developed a technique that provides a full range of organization of works on programming the MDR32F9Q2I microcontroller, which allows you to obtain control and monitoring systems for secondary power supply sources. The microcontroller based on the high-performance ARM RISC processor core was programmed in the Eclipse IDE on the Windows 10 Pro operating system. We chose the Eclipse integrated development environment as the most convenient and accessible environment, it supports all kinds of programming languages and continuous compilation. Currently, 16- and 32-bit microcontrollers are rapidly gaining popularity in the field of industrial tasks. Their use is due to the ever-increasing complexity of tasks, stringent requirements for the performance of integrated controllers, the need to have advanced user controls in electronic devices. We present a simulation stand that uses an interface bridge between the I2C and 1-Wire buses - DS2482-100, converts protocols between the I2C microcontroller (master) and 1-Wire slaves, and also controls the voltage rise and fall rates in the line. The basis for writing the DS2482 class is the Arduino.h and OneWire.h header files, which are freely available

The Design of a 2D Graphics Accelerator for Embedded Systems

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

Development of Control Module Based on a Computing IP-Core

The article presents the result of the implementation of a synthesized microcontroller in integrated circuits of small FPGAs and a variant of building a control system for an onboard control module based on the developed solution. The possibility of creating a full-fledged microcontroller based on a type 5578TC034 FPGA and more capacious microcontrollers is shown. The description of the structure of the microcontroller, processor core and periphery is given. The processor instruction system is presented. Ip-modules of peripheral devices and some interfaces have been developed. A variant of creating a control system using the developed microcontroller is proposed. In the future, it is planned to increase the functionality of the synthesized microcontroller by optimizing ip-modules and adding new ones. When developing the control system, a domestic component base was used.