Shared Buffer Crossbar Architecture for GPU-CPU

Mapping Intimacies ◽

10.1007/978-981-16-0275-7_60 ◽

2021 ◽

pp. 735-745

Author(s):

Deepika Pitliya ◽

Namita Palecha

Keyword(s):

Crossbar Architecture ◽

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An approximate transient analysis of dynamic thresholds in an ATM switch with shared buffer memory

Electronics and Communications in Japan (Part I Communications) ◽

10.1002/1520-6424(200106)84:6<1::aid-ecja1>3.0.co;2-5 ◽

2001 ◽

Vol 84 (6) ◽

pp. 1-10

Author(s):

Tetsuo Zouta ◽

Hiroshi Inai ◽

Jiro Yamakita

Keyword(s):

Transient Analysis ◽

Buffer Memory ◽

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Banyan multipath self-routing ATM switches with shared buffer type switch elements

IEEE Transactions on Communications ◽

10.1109/26.481235 ◽

1995 ◽

Vol 43 (11) ◽

pp. 2847-2857 ◽

Author(s):

Youn Chan Jung ◽

Chong-Kwan Un

Keyword(s):

Type Switch ◽

Atm Switches ◽

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Improved queueing analysis of shared buffer switching networks

IEEE INFOCOM '93 The Conference on Computer Communications, Proceedings ◽

10.1109/infcom.1993.253404 ◽

2002 ◽

Author(s):

G. Bianchi ◽

J.S. Turner

Keyword(s):

Queueing Analysis ◽

Switching Networks ◽

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Reliable logic design with defective nano-crossbar architecture

2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) ◽

10.1109/discover.2016.7806231 ◽

2016 ◽

Author(s):

Malay Kule ◽

Hafizur Rahaman ◽

Bhargab B. Bhattacharya

Keyword(s):

Logic Design ◽

Crossbar Architecture

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Shared Buffer Approach in Fault Tolerant Networks

2009 International Conference on Computer Technology and Development ◽

10.1109/icctd.2009.19 ◽

2009 ◽

Author(s):

Luisito I. Tabada ◽

Pierre U. Tagle

Keyword(s):

Fault Tolerant ◽

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ANALYTICAL PERFORMANCE EVALUATION OF SMALL FLOW LINES WITH SHARED BUFFER

IFAC Proceedings Volumes ◽

10.3182/20070613-3-fr-4909.00004 ◽

2007 ◽

Vol 40 (6) ◽

pp. 7-12

Author(s):

Davide Ferrari ◽

Andrea Matta

Keyword(s):

Performance Evaluation ◽

Analytical Performance ◽

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A Diagonally Weighted Binary Memristor Crossbar Architecture Based on Multilayer Neural Network for Better Accuracy Rate in Speech Recognition Application

Advances in Electrical and Computer Engineering ◽

10.4316/aece.2019.02010 ◽

2019 ◽

Vol 19 (2) ◽

pp. 75-82

Author(s):

M.-H. VO

Keyword(s):

Neural Network ◽

Speech Recognition ◽

Accuracy Rate ◽

Crossbar Architecture ◽

Memristor Crossbar

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DESIGN OF SHARED BUFFER ARCHITECTURE FOR CPU-GPU ON CHIP NETWORK

INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING AND TECHNOLOGY ◽

10.34218/ijeet.11.4.2020.041 ◽

2020 ◽

Vol 11 (4) ◽

Author(s):

DEEPIKA PITLIYA ◽

NAMITA PALECHA

Keyword(s):

On Chip ◽

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Dynamic thresholds for shared buffer switches with variable length packets

Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie ◽

10.1109/hpsr.2002.1024225 ◽

2003 ◽

Author(s):

Ruey-Bin Yang ◽

Ming-Cheng Liang ◽

Yuan-Sun Chu ◽

Cheng-Shong Wu

Keyword(s):

Variable Length ◽

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Approximate Analysis of a Discrete-Time Queueing Model of the Shared Buffer ATM Switch

Linear Algebra, Markov Chains, and Queueing Models - The IMA Volumes in Mathematics and its Applications ◽

10.1007/978-1-4613-8351-2_14 ◽

1993 ◽

pp. 211-229

Author(s):

S. Hong ◽

H. G. Perros ◽

H. Yamashita

Keyword(s):

Discrete Time ◽

Queueing Model ◽

Approximate Analysis ◽

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