Formal verification of digital circuits using symbolic ternary system models

Lecture Notes in Computer Science - Computer-Aided Verification ◽

10.1007/bfb0023717 ◽

2005 ◽

pp. 33-43 ◽

Cited By ~ 15

Author(s):

Randal E. Bryant ◽

Carl-Johan H. Seger

Keyword(s):

Ternary System ◽

Formal Verification ◽

Digital Circuits ◽

System Models

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Formal verification of digital circuits using symbolic ternary system models

Computer-Aided Verification ’90 - DIMACS Series in Discrete Mathematics and Theoretical Computer Science ◽

10.1090/dimacs/003/11 ◽

1991 ◽

pp. 121-146 ◽

Cited By ~ 5

Author(s):

R. Bryant ◽

C.-J. Seger

Keyword(s):

Ternary System ◽

Formal Verification ◽

Digital Circuits ◽

System Models

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Introducing Digital Circuits Design and Formal Verification Concurrently

Microelectronics Education ◽

10.1007/978-94-015-9506-3_60 ◽

2000 ◽

pp. 261-264 ◽

Cited By ~ 2

Author(s):

Paul Amblard ◽

Fabienne Lagnier ◽

Michel Levy

Keyword(s):

Formal Verification ◽

Digital Circuits

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A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.29-32.1040 ◽

2010 ◽

Vol 29-32 ◽

pp. 1040-1045

Author(s):

Zhong Liang Pan ◽

Ling Chen

Keyword(s):

Formal Verification ◽

Circuit Design ◽

Digital Circuits ◽

Experimental Results ◽

Equivalence Checking ◽

Decision Diagrams ◽

Circuit Partitioning ◽

Circuit Verification ◽

Verification Method ◽

Signal Line

The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The verification procedure is to compare the equivalence of the multiple-valued decision diagrams of two types of cone structures. Experimental results on a lot of benchmark circuits show the method presented in this paper can effectively perform the equivalence checking of circuits.

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