Test generation for digital circuits described by means of register transfer languages

1987 ◽  
Vol 134 (2) ◽  
pp. 69 ◽  
Author(s):  
E. Villar ◽  
S. Bracho
Keyword(s):  
Test Generation ◽  
Digital Circuits ◽  
Register Transfer

scholarly journals Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Anand V. Hudli ◽  
Raghu V. Hudli
Keyword(s):  
Temporal Logic ◽  
Test Generation ◽  
Digital Circuits ◽  
Difficult Problem ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Temporal Behavior ◽  
Generation Algorithm

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

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