An arithmetic approach to the analysis of multiple faults verification and synthesis at switch-level

Switch-level modeling and simulation has become an important method of predicting the behaviour of CMOS circuits under the presence of faults. Many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength can be reliably modeled using this technique. This paper presents an algorithm for modeling directional and bi-directional CMOS circuits with an arithmetic solution for circuit verification and fault synthesis. This new approach is capable of simulating multiple fault injection into the circuit and speeds up switch-level simulation. Other advantages of this algorithm are its application in the mapping of single and multiple faults from switch level to gate level and the ability to function as a multi-level model. Multiple faults can be of the same or different types. Experimental results using Cadence tools show that the algorithm is successful and reliable for CMOS technology.

An arithmetic approach to the analysis of multiple faults verification and synthesis at switch-level

Switch-level modeling and simulation has become an important method of predicting the behaviour of CMOS circuits under the presence of faults. Many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength can be reliably modeled using this technique. This paper presents an algorithm for modeling directional and bi-directional CMOS circuits with an arithmetic solution for circuit verification and fault synthesis. This new approach is capable of simulating multiple fault injection into the circuit and speeds up switch-level simulation. Other advantages of this algorithm are its application in the mapping of single and multiple faults from switch level to gate level and the ability to function as a multi-level model. Multiple faults can be of the same or different types. Experimental results using Cadence tools show that the algorithm is successful and reliable for CMOS technology.

Rewriting Environment for Arithmetic Circuit Verification

The paper describes a practical software tool for the verification of integer arithmetic circuits. It covers different types of integer multipliers, fused add-multiply circuits, and constant dividers - in general, circuits whose computation can be represented as a polynomial. The verification uses an algebraic model of the circuit and is accomplished by rewriting the polynomial of the binary encoding of the primary outputs (output signature), using the polynomial models of the logic gates, into a polynomial over the primary inputs (input signature). The resulting polynomial represents arithmetic function implemented by the circuit and hence can be used to extract functional specification from its gate-level implementation. The rewriting uses an efficient And-Inverter Graph (AIG) representation to enable extraction of the essential arithmetic components of the circuit. The tool is integrated with the popular ABC system. Its efficiency is illustrated with impressive results for integer multipliers, fused add-multiply circuits, and divide-by-constant circuits. The entire verification system is offered in an open source ABC environment together with an extensive set of benchmarks.