Efficient fault tolerant cache memory design

Microprocessing and Microprogramming ◽

10.1016/0165-6074(95)00004-8 ◽

1995 ◽

Vol 41 (2) ◽

pp. 153-169 ◽

Author(s):

H.T. Verges ◽

D. Nikolos

Keyword(s):

Fault Tolerant ◽

Cache Memory ◽

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Cache tag RAM chips simplify cache memory design

Microprocessors and Microsystems ◽

10.1016/0141-9331(90)90013-l ◽

1990 ◽

Vol 14 (1) ◽

pp. 47-57 ◽

Author(s):

David C Wyland

Keyword(s):

Cache Memory ◽

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Cache memory design for network processors

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550) ◽

10.1109/hpca.2000.824369 ◽

2002 ◽

Author(s):

Tzi-Cker Chiueh ◽

P. Pradhan

Keyword(s):

Cache Memory ◽

Network Processors ◽

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A fast low power embedded cache memory design

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) ◽

10.1109/icasic.2001.982626 ◽

2002 ◽

Author(s):

Zhao Xue-mei ◽

Ye Yi-zheng ◽

Yu Ming-yan ◽

Li Xiao-ming

Keyword(s):

Low Power ◽

Cache Memory ◽

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Cellular automata based fault tolerant resistive memory design

2016 Sixth International Symposium on Embedded Computing and System Design (ISED) ◽

10.1109/ised.2016.7977077 ◽

2016 ◽

Author(s):

Mousumi Saha ◽

Sutapa Sarkar ◽

Biplab K Sikdar

Keyword(s):

Cellular Automata ◽

Fault Tolerant ◽

Resistive Memory ◽

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Josephson 4 K‐bit cache memory design for a prototype signal processor. III. Decoding, sensing, and timing

Journal of Applied Physics ◽

10.1063/1.336303 ◽

1985 ◽

Vol 58 (6) ◽

pp. 2389-2399 ◽

Author(s):

W. H. Henkels ◽

L. M. Geppert ◽

J. Kadlec ◽

P. W. Epperlein ◽

H. Beha ◽

...

Keyword(s):

Cache Memory ◽

Memory Design ◽

Signal Processor

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Josephson 4 K‐bit cache memory design for a prototype signal processor. II. Cell array and drivers

Journal of Applied Physics ◽

10.1063/1.335961 ◽

1985 ◽

Vol 58 (6) ◽

pp. 2379-2388 ◽

Author(s):

W. H. Henkels ◽

L. M. Geppert ◽

J. Kadlec ◽

P. W. Epperlein ◽

H. Beha ◽

...

Keyword(s):

Cache Memory ◽

Memory Design ◽

Signal Processor

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Fault tolerant memory design for HW/SW co-reliability in massively parallel computing systems

Second IEEE International Symposium on Network Computing and Applications, 2003. NCA 2003. ◽

10.1109/nca.2003.1201173 ◽

2003 ◽

Author(s):

M. Choi ◽

N.-J. Park ◽

K.M. George ◽

B. Jin ◽

N. Park ◽

...

Keyword(s):

Parallel Computing ◽

Fault Tolerant ◽

Massively Parallel ◽

Computing Systems ◽

Memory Design ◽

Massively Parallel Computing

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Fault-tolerant memory design in the IBM application system/400

[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium ◽

10.1109/ftcs.1991.146691 ◽

2002 ◽

Author(s):

C.L. Chen ◽

L.E. Grosbach

Keyword(s):

Fault Tolerant ◽

Application System ◽

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Defect-tolerant cache memory design

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium ◽

10.1109/vtest.1993.313331 ◽

2002 ◽

Author(s):

D. Lamet ◽

J.F. Frenzel

Keyword(s):

Cache Memory ◽

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Cache memory design: an evolving art

Microprocessors and Microsystems ◽

10.1016/0141-9331(88)90057-9 ◽

1988 ◽

Vol 12 (2) ◽

pp. 114

Keyword(s):

Cache Memory ◽

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