Constant time fault tolerant algorithms for a linear array with a reconfigurable pipelined bus system

2005 ◽  
Vol 65 (3) ◽  
pp. 374-381 ◽  
Author(s):  
Anu G. Bourgeois ◽  
Yi Pan ◽  
Sushil K. Prasad
1993 ◽  
Vol 03 (02) ◽  
pp. 157-164 ◽  
Author(s):  
P. THANGAVEL ◽  
V.P. MUTHUSWAMY

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.


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