A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM

1993 ◽  
Vol 03 (02) ◽  
pp. 157-164 ◽  
Author(s):  
P. THANGAVEL ◽  
V.P. MUTHUSWAMY
Keyword(s):  
Parallel Algorithm ◽  
Linear Array ◽  
Constant Time ◽  
Processor Array ◽  
Gray Codes ◽  
System A ◽  
Processor Arrays ◽  
Bus System

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

ON THE POWER OF TWO-DIMENSIONAL PROCESSOR ARRAYS WITH RECONFIGURABLE BUS SYSTEMS

1991 ◽  
Vol 01 (01) ◽  
pp. 29-34 ◽  
Author(s):  
STEPHAN OLARIU ◽  
JAMES L. SCHWING ◽  
JINGYUAN ZHANG
Keyword(s):  
Shared Memory ◽  
Constant Time ◽  
Processor Array ◽  
Two Dimensional ◽  
Parity Problem ◽  
Processor Arrays ◽  
Bus System

Quite recently it has been proved that a two-dimensional processor array with a reconfigurable bus system (PARBS, for short) is at least as powerful as the CRCW shared memory computer. In this note we argue that the well-known PARITY problem can be solved in O(1) time on a two-dimensional PARBS of (n+1)×n processors. Since it is known that PARITY cannot be solved in constant time on a CRCW even if a polynomial number of processors is available, our result shows that the two-dimensional PARBS is strictly more powerful than the CRCW.

A CONSTANT TIME ALGORITHM FOR REDUNDANCY ELIMINATION IN TASK GRAPHS ON PROCESSOR ARRAYS WITH RECONFIGURABLE BUS SYSTEMS

1993 ◽  
Vol 03 (02) ◽  
pp. 171-177 ◽  
Author(s):  
B. PRADEEP ◽  
C. SIVA RAM MURTHY
Keyword(s):  
Parallel Algorithm ◽  
Time Algorithm ◽  
Constant Time ◽  
Redundancy Elimination ◽  
Task Graphs ◽  
Processor Arrays ◽  
Precedence Graph ◽  
Practical Tool ◽  
Algorithm Parallelization

The task or precedence graph formalism is a practical tool to study algorithm parallelization. Redundancy in such task graphs gives rise to numerous avoidable inter-task dependencies which invariably complicates the process of parallelization. In this paper we present an O(1) time algorithm for the elimination of redundancy in such graphs on Processor Arrays with Reconfigurable Bus Systemusing O(n4) processors, The previous parallel algorithm available in the literature for redundancy elimination in task graphs takes O(n2) time using O(n) processors.

GENERATING n-ARY REFLECTED GRAY CODES ON A LINEAR ARRAY OF PROCESSORS

1996 ◽  
Vol 06 (01) ◽  
pp. 27-34 ◽  
Author(s):  
IVAN STOJMENOVIC
Keyword(s):  
Parallel Algorithm ◽  
Arbitrary Number ◽  
Linear Array ◽  
Gray Code ◽  
Gray Codes ◽  
Model Of Computation ◽  
Constant Size

We present a cost-optimal parallel algorithm for generating n-ary reflected Gray codes, i.e. variations of m elements out of {0, 1,…, n–1} in a Gray code order. It uses a linear array of m processors, each having constant size memory and each being responsible for producing one part of a given variation. The algorithm is simple and uses a weaker model of computation than a recently published algorithm. In addition, it can be made adaptive (i.e. to run on a linear array with an arbitrary number of processors) and can be generalized to produce variations out of an arbitrary set of elements.

ON THE EFFICIENT SUMMATION OF N NUMBERS ON AN N-PROCESSOR RECONFIGURABLE MESH

1993 ◽  
Vol 03 (01) ◽  
pp. 71-78 ◽  
Author(s):  
PARASKEVI FRAGOPOULOU
Keyword(s):  
Parallel Algorithm ◽  
Processor Array ◽  
Two Dimensional ◽  
Reconfigurable Mesh ◽  
The Given ◽  
Prefix Sums ◽  
Bus System

A reconfigurable mesh is a two-dimensional processor array equipped with a reconfigurable bus system that can be changed dynamically to suit different computational needs. In this paper we present a parallel algorithm for the summation of N numbers each in the range [0, 2b). The algorithm runs in O(b+ log log N) time on [Formula: see text] reconfigurable mesh. This is an improvement over the best previously known algorithm that solves the same problem in O(b log log N) time. The algorithm is finally extended to compute the prefix sums of the given numbers in the same time.

scholarly journals Constant time sorting on a processor array with a reconfigurable bus system

1990 ◽  
Vol 34 (4) ◽  
pp. 187-192 ◽  
Author(s):  
Biing-Feng Wang ◽  
Gen-Huey Chen ◽  
Ferng-Ching Lin
Keyword(s):  
Constant Time ◽  
Processor Array ◽  
Bus System

DESIGNING A SYSTOLIC ALGORITHM FOR GENERATING WELL-FORMED PARENTHESIS STRINGS

2004 ◽  
Vol 14 (01) ◽  
pp. 83-97
Author(s):  
JONG-CHUANG TSAY
Keyword(s):  
Linear Array ◽  
Vlsi Implementation ◽  
Processor Array ◽  
Lexicographical Order ◽  
Systolic Algorithm ◽  
Left And Right ◽  
Local Connection

A parenthesis string is a string of left and right parentheses. The string is well-formed when it consists of balanced pairs of left and right parentheses. This study presents a novel systolic algorithm for generating all the well-formed parenthesis strings in lexicographical order. The algorithm is cost-optimal and is run on a linear array of processors such that each well-formed parenthesis string can be generated in three time steps. The processor array is appropriate for VLSI implementation, since it has the features of modularity, regularity, and local connection.

Sign in / Sign up

Export Citation Format

Share Document