MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET

Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

Plasmonic nanostructures for shrinking structured light to access forbidden transitions

Plasmonic nanostructures have considerable applicability in light–matter interactions owing to their capacity for strong field confinement and enhancement. Nanogap structures allow us to tailor electric field distributions at the nanoscale, bridging the differences in size and shape of atomic and light structures. In this study, we demonstrated that a plasmonic tetramer structure can squeeze structured light into a nanoscale area, in which a strong field gradient allows access to forbidden transitions. Numerical simulations showed that the gold tetramer structure on a glass substrate possesses a plasmonic eigenmode, which forms structured light with a quadrupole profile in the nanogap region at the center of the tetramer. The top–down technique employed using electron-beam lithography allows us to produce a gap size of approximately 50 nm, which supports plasmonic resonance in the near-infrared regime. In addition, we demonstrated an array architecture in which a collective lattice resonance enhances the intensity of the quadrupole field in multiple lattice units. This study highlights the possibility of accessing multipolar transitions in a combined system of structured light and plasmonic nanostructures. Our findings may lead to new platforms for spectroscopy, sensing, and light sources that take advantage of the full electronic spectrum of an emitter.

Bio-acoustic tracking and localization using heterogeneous, scalable microphone arrays

Microphone arrays are an essential tool in the field of bioacoustics as they provide a non-intrusive way to study animal vocalizations and monitor their movement and behavior. Microphone arrays can be used for passive localization and tracking of sound sources while analyzing beamforming or spatial filtering of the emitted sound. Studying free roaming animals usually requires setting up equipment over large areas and attaching a tracking device to the animal which may alter their behavior. However, monitoring vocalizing animals through arrays of microphones, spatially distributed over their habitat has the advantage that unrestricted/unmanipulated animals can be observed. Important insights have been achieved through the use of microphone arrays, such as the convergent acoustic field of view in echolocating bats or context-dependent functions of avian duets. Here we show the development and application of large flexible microphone arrays that can be used to localize and track any vocalizing animal and study their bio-acoustic behavior. In a first experiment with hunting pallid bats the acoustic data acquired from a dense array with 64 microphones revealed details of the bats’ echolocation beam in previously unseen resolution. We also demonstrate the flexibility of the proposed microphone array system in a second experiment, where we used a different array architecture allowing to simultaneously localize several species of vocalizing songbirds in a radius of 75 m. Our technology makes it possible to do longer measurement campaigns over larger areas studying changing habitats and providing new insights for habitat conservation. The flexible nature of the technology also makes it possible to create dense microphone arrays that can enhance our understanding in various fields of bioacoustics and can help to tackle the analytics of complex behaviors of vocalizing animals.

Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation

Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory access and data migration between on-chip buffer and off-chip DRAM is even much more than the computation energy on processing element array (PE array). In order to reduce the energy consumption of memory access, a better dataflow to maximize data reuse and minimize data migration between on-chip buffer and external DRAM is important. Especially, the dimension of input feature map (ifmap) and filter weight are much different for each layer of the neural network. Hardware resources may not be effectively utilized if the array architecture and dataflow cannot be reconfigured layer by layer according to their ifmap dimension and filter dimension, and result in a large quantity of data migration on certain layers. However, a thorough exploration of all possible configurations is time consuming and meaningless. In this paper, we propose a quick and efficient methodology to adapt the configuration of PE array architecture, buffer assignment, dataflow and reuse methodology layer by layer with the given CNN architecture and hardware resource. In addition, we make an exploration on the different combinations of configuration issues to investigate their effectiveness and can be used as a guide to speed up the thorough exploration process.

Switchable Multifunctional Meta-Surface Composed by Dielectric-Metal Hybrid Antenna Array Architecture

Strontium titanate (STO), the dielectric material, has caught the world’s attention due to its outstanding properties, such as high permittivity, high refractive index, and low loss in the terahertz band. Its permittivity is relevant to the environment temperature. Herein, a multifunctional meta-surface composed of a dielectric-metal hybrid antenna array has been demonstrated, which is a single-layer STO elliptic cylinder. On the one hand, when the environment temperature is 300 K, the proposed meta-surface can achieve perfect absorption and polarization conversion in the frequency range from 0.1 to 0.25 THz; particularly, the meta-surface absorptance can reach 99.97% and 99.92% at a frequency of 0.103 and 0.13 THz respectively, and while it is used as a polarization conversion device, the degree of circular polarization and the ellipticity angle can reach 0.986 and 44.5° at a frequency of 0.228 THz. On the other hand, when the environment temperature changes from 300 to 450 K, the absorption peak changes with the temperature, and the average absorptance reaches 96% at resonance frequency. The proposed meta-surface can be applied in many fields, such as optical sensing, imaging, and energy harvesting. Moreover, it provides a potential solution to research the integrated device in a complex electromagnetic environment.

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient integration of the obfuscation technique, while maintaining low overheads. The algorithms for these two transforms were restructured in such a way that their structures are fairly similar, and thus they can be implemented on the same VLSI chip and on the same hardware with very few modifications, with the latter being attributed to the pre-processing and post-processing stages. The design proposed uses the regular and modular structures, which are named quasi-correlation, and the architecture is inspired by the paradigm of the systolic array architecture. Thus, the introduced design benefits the security, for the hardware, and also the advantages introduced by the use of the regular and modular structures. A very efficient, unified VLSI architecture for type IV DCT/DST can be obtained, which allows the computation of the two algorithms on the same hardware, allowing an efficient incorporation of the obfuscation technique with very low overheads, and it can be very efficiently implemented, offering high-speed performances and low hardware complexity, with the latter being attributed to the efficient use of the hardware resources for the computation of these two algorithms.

Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks

The systolic array architecture is one of the most popular choices for convolutional neural network hardware accelerators. The biggest advantage of the systolic array architecture is its simple and efficient design principle. Without complicated control and dataflow, hardware accelerators with the systolic array can calculate traditional convolution very efficiently. However, this advantage also brings new challenges to the systolic array. When computing special types of convolution, such as the small-scale convolution or depthwise convolution, the processing element (PE) utilization rate of the array decreases sharply. The main reason is that the simple architecture design limits the flexibility of the systolic array. In this article, we design a configurable multi-directional systolic array (CMSA) to address these issues. First, we added a data path to the systolic array. It allows users to split the systolic array through configuration to speed up the calculation of small-scale convolution. Second, we redesigned the PE unit so that the array has multiple data transmission modes and dataflow strategies. This allows users to switch the dataflow of the PE array to speed up the calculation of depthwise convolution. In addition, unlike other works, we only make a few changes and modifications to the existing systolic array architecture. It avoids additional hardware overheads and can be easily deployed in application scenarios that require small systolic arrays such as mobile terminals. Based on our evaluation, CMSA can increase the PE utilization rate by up to 1.6 times compared to the typical systolic array when running the last layers of ResNet-18. When running depthwise convolution in MobileNet, CMSA can increase the utilization rate by up to 14.8 times. At the same time, CMSA and the traditional systolic arrays are similar in area and energy consumption.

Transfer Modeling for 1T1R Crossbar Arrays with Line Resistances

Progress of neuromorphic computing and next-generation information storage technologies hinges on the development of emerging nonvolatile memory (eNVM) devices, which are typically organized employing the crossbar array architecture. To facilitate quantitative performance analysis of eNVM crossbar array architecture, this paper proposes a way to study the one-transistor-one-resistor (1T1R, R: eNVM devices) crossbar arrays based on matrix algebra method. The comparative analysis of 1T1R crossbar array modeling based on matrix algebra method and compact-model SPICE simulations verifies the accuracy of the proposed method, which can be directly used for static quantitative analysis and evaluation of 1T1R crossbar array performance. With the proposed method, the optimization of array operation schemes and current backflow issue are discussed. Our analysis indicates that the proposed method is capable of flexibly adjusting array parameters and consider the influence of line resistance on array operation, and can provide guidance for improving the sensing margin of the array through multi-parameter co-simulation. The proposed matrix algebra-based 1T1R crossbar array modeling method can bridge the gap between the accuracy and flexibility of the available methods.