Efficient FPGA Implementation and Verification of Difference Expansion Based Reversible Watermarking with Improved Time and Resource Utilization

2021 ◽  
pp. 103732
Author(s):  
Subhajit Das ◽  
Arun Kumar Sunaniya ◽  
Reshmi Maity ◽  
Niladri Pratap Maity
Keyword(s):  
Resource Utilization ◽  
Reversible Watermarking ◽  
Fpga Implementation ◽  
Difference Expansion

FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time

2017 ◽  
Vol 14 (1) ◽  
pp. 193-221 ◽  
Author(s):  
Sambaran Hazra ◽  
Sudip Ghosh ◽  
Sayandip De ◽  
Hafizur Rahaman
Keyword(s):  
Real Time ◽  
Reversible Watermarking ◽  
Fpga Implementation

An Implementation and Improvement of Fast Two-Dimensional Median Filtering

2011 ◽  
Vol 55-57 ◽  
pp. 95-100
Author(s):  
Gui Tang Wang ◽  
Rui Huang Wang ◽  
Feng Wang ◽  
Wen Juan Liu
Keyword(s):  
Detailed Analysis ◽  
Resource Utilization ◽  
Fpga Implementation ◽  
Median Filtering ◽  
Two Dimensional ◽  
Occupancy Rate ◽  
Filtering Algorithm ◽  
Comparison Of Results

This paper discussed a conventional fast median filtering algorithm for FPGA implementation. An improved way -- Quasi-median filtering algorithm -- have been proposed to reduce the occupancy rate of FPGA resources on the premise of ensuring the result of median filtering. Through the detailed analysis and comparison of results of simulation and experiments, conclusions can be drawn that such improvements can achieve better filtering results, and can reduce FPGA resource utilization. It offers some value for the application of design which requires more FPGA resources.

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