scholarly journals Design of High Speed Data Acquisition System for Linear Array CCD Based on FPGA

2020 ◽  
Vol 166 ◽  
pp. 414-418 ◽  
Author(s):  
Si Yong Fu
2014 ◽  
Vol 556-562 ◽  
pp. 1515-1519 ◽  
Author(s):  
Zhi Li ◽  
Da Hua Chen

High speed analog signals output by test object in the field of testing and controlling is typical. This paper designed a high-speed AD data acquisition system responding to this situation. In the design of the system, data is first conditioned by the analog channel. FPGA is then employed to receive, decelerate, reorganize and store the high-speed LVDS data output by AD. Data is displayed in computer after being collected by ARM from FGPA. Real circuit designing demonstrated that the high-speed data acquisition system of AD based on 100M bandwidth of analog channel is workable.


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