A memory-efficient parameterisable FPGA implementation of the cdma2000 turbo codec

Author(s):  
E. Brown ◽  
J. Irvine ◽  
B. Wilkie
2018 ◽  
Vol 12 (10) ◽  
pp. 1753-1761 ◽  
Author(s):  
Vineet Kumar ◽  
Abhijit Asati ◽  
Anu Gupta

2013 ◽  
Vol 380-384 ◽  
pp. 3328-3331
Author(s):  
Jian Bing Han ◽  
Chen He ◽  
Ran Zhen

This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.


2013 ◽  
Vol 5 (1) ◽  
pp. 36-41
Author(s):  
R. Ganesh ◽  
◽  
Ch. Sandeep Reddy ◽  

Author(s):  
Jeniffer A ◽  
Haripasath S ◽  
Chinthamani S ◽  
Chitra G ◽  
Karthiga V

2019 ◽  
Vol 12 (1) ◽  
pp. 1 ◽  
Author(s):  
Badr El Kari ◽  
Hassan Ayad ◽  
Abdeljalil El Kari ◽  
Mostafa Mjahed ◽  
Claudiu Pozna

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