Low-loss design method for a planar dielectric-waveguide branch: effect of a taper of serpentine shape

1991 ◽  
Vol 39 (1) ◽  
pp. 6-13 ◽  
Author(s):  
M. Tsuji ◽  
O. Tanaka ◽  
H. Shigesawa
Keyword(s):  
Dielectric Waveguide ◽  
Design Method ◽  
Low Loss ◽  
Planar Dielectric Waveguide

Scattering of eigenmodes of planar dielectric waveguide with PEC wall by graphene strip grating at THz

2021 ◽  
pp. 1-18
Author(s):  
Mstislav E. Kaliberda ◽  
Leonid M. Lytvynenko ◽  
Sergey A. Pogarsky
Keyword(s):  
Dielectric Waveguide ◽  
Planar Dielectric Waveguide ◽  
Graphene Strip

New design method for low-loss Y-branch waveguides

2001 ◽  
Vol 19 (9) ◽  
pp. 1376-1384 ◽  
Author(s):  
T. Yabu ◽  
M. Geshiro ◽  
S. Sawa
Keyword(s):  
Design Method ◽  
Low Loss

A Low-Loss and High-Isolation Transformer-Based mm-Wave SPDT with Integrated Fan-out Wafer Level Packaging

2019 ◽  
Vol 29 (07) ◽  
pp. 2050115
Author(s):  
Xing Quan ◽  
Jiang Luo ◽  
Guodong Su ◽  
Kai Jing ◽  
Jinsong Zhan
Keyword(s):  
Design Method ◽  
Control Device ◽  
Secondary Coil ◽  
Cmos Process ◽  
Wafer Level ◽  
Low Loss ◽  
High Isolation ◽  
Wafer Level Packaging ◽  
Isolation Transformer ◽  
Better Than

This paper proposes a low-loss and high-isolation transformer (TF)-based mm-wave single-pole double-throw (SPDT) switch. The center-tapped technique is employed at the secondary coil of TF to improve isolation performance. The TF is implemented with the metals in redistribution layers (RDLs) in integrated fan-out (InFO) wafer level packaging technology to obtain low insertion loss (IL) and small chip size as the TF usually dominates the area of SPDT. The control device of the SPDT is realized in 40[Formula: see text]nm bulk CMOS process. The simulated result shows the proposed SPDT achieves a minimum IL of 1.34[Formula: see text]dB and the IL is less than 2.2[Formula: see text]dB at 24–31[Formula: see text]GHz. The isolations are better than 27[Formula: see text]dB between two double-throw ports and better than 20[Formula: see text]dB between single-pole and double-throw ports, respectively. The proposed SPDT has a compact silicon size of 220[Formula: see text][Formula: see text] (with PADs) and its return losses are better than [Formula: see text]9[Formula: see text]dB at 24–31[Formula: see text]GHz and. This work explores a new chip-package co-design method for the SPDT and may have some guidance for the co-design of SPDT and antenna in package (AiP).

Transmission Characteristics Of The Electrooptically Perturbated Planar Dielectric Waveguide

1987 ◽  
Author(s):  
Andrzej W. Domanski ◽  
Wieslaw Krolikowski
Keyword(s):  
Dielectric Waveguide ◽  
Transmission Characteristics ◽  
Planar Dielectric Waveguide
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