We present a new parallel sorting algorithm that uses a fixed-size sorter iteratively to
sort inputs of arbitrary size. A parallel sorting architecture based on this algorithm is
proposed. This architecture consists of three components, linear arrays that support
constant-time operations, a multilevel sorting network, and a termination detection tree,
all operating concurrently in systolic processing fashion. The structure of this sorting
architecture is simple and regular, highly suitable for VLSI realization. Theoretical
analysis and experimental data indicate that the performance of this architecture is
likely to be excellent in practice.
An Efficient Parallel VLSI Sorting Architecture
