A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power
2019 ◽
Vol 54
(11)
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pp. 3149-3160
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2010 ◽
Vol 130
(5)
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pp. 479-480
2015 ◽
Vol 03
(06)
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pp. 5083-5089
2010 ◽
Vol E93-B
(7)
◽
pp. 1788-1796
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Keyword(s):
2006 ◽
Vol 10
(2)
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pp. 129-155
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