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Core interconnect testing hazards
Proceedings Design, Automation and Test in Europe
◽
10.1109/date.1998.655985
◽
2002
◽
Author(s):
P. Nordholz
◽
H. Grabinski
◽
D. Treytnar
◽
J. Otterstedt
◽
D. Niggemeyer
◽
...
Keyword(s):
Interconnect Testing
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Development of Cloud Service for Interconnect Testing on HEMS Devices
IEEJ Transactions on Electronics Information and Systems
◽
10.1541/ieejeiss.133.818
◽
2013
◽
Vol 133
(4)
◽
pp. 818-819
Author(s):
Hiroshi Sugimura
◽
Kazuo Sekiya
◽
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Interconnect Testing for Networks on Chips
24th IEEE VLSI Test Symposium
◽
10.1109/vts.2006.41
◽
2006
◽
Cited By ~ 25
Author(s):
K. Stewart
◽
S. Tragoudas
Keyword(s):
Interconnect Testing
◽
Networks On Chips
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FPGA test time reduction through a novel interconnect testing scheme
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02
◽
10.1145/503048.503069
◽
2002
◽
Cited By ~ 8
Author(s):
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◽
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Keyword(s):
Test Time
◽
Interconnect Testing
◽
Testing Scheme
◽
Test Time Reduction
◽
Time Reduction
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Adapting jtag for ac interconnect testing
International Test Conference, 2003. Proceedings. ITC 2003.
◽
10.1109/test.2003.1270892
◽
2004
◽
Cited By ~ 2
Author(s):
L. Whetsel
Keyword(s):
Interconnect Testing
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BIST and interconnect testing with boundary scan
IEEE Proceedings of the SOUTHEASTCON '91
◽
10.1109/secon.1991.147692
◽
2002
◽
Cited By ~ 4
Author(s):
A.A. Setty
◽
H.L. Martin
Keyword(s):
Boundary Scan
◽
Interconnect Testing
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Embedded Memory Interface Logic and Interconnect Testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2014.2354381
◽
2015
◽
Vol 23
(9)
◽
pp. 1946-1950
◽
Cited By ~ 2
Author(s):
Baker Mohammad
Keyword(s):
Embedded Memory
◽
Interconnect Testing
◽
Memory Interface
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A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip
2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
◽
10.1109/dft.2010.21
◽
2010
◽
Cited By ~ 2
Author(s):
Min-Ju Chan
◽
Chun-Lung Hsu
Keyword(s):
Network On Chip
◽
Mesh Network
◽
Interconnect Testing
◽
On Chip
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Implementation of boundary-scan architecture and its application to module interconnect testing
10.14711/thesis-b603889
◽
1998
◽
Author(s):
Chun Keung Lo
Keyword(s):
Boundary Scan
◽
Interconnect Testing
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Automated boundary-scan diagnostics: adding value to interconnect testing
Conference Record AUTOTESTCON '92: The IEEE Systems Readiness Technology Conference
◽
10.1109/autest.1992.270090
◽
2003
◽
Cited By ~ 2
Author(s):
J.D. Milgram
Keyword(s):
Boundary Scan
◽
Interconnect Testing
Download Full-text
A sweeping line approach to interconnect testing
IEEE Transactions on Computers
◽
10.1109/12.536234
◽
1996
◽
Vol 45
(8)
◽
pp. 917-929
◽
Cited By ~ 9
Author(s):
J. Salinas
◽
Yinan Shen
◽
F. Lombardi
Keyword(s):
Interconnect Testing
Download Full-text
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