24th IEEE VLSI Test Symposium
Latest Publications

TOTAL DOCUMENTS

91

(FIVE YEARS 0)

H-INDEX

14

(FIVE YEARS 0)

Published By IEEE

0769525148

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Interconnect Testing for Networks on Chips

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.41 ◽

2006 ◽

Cited By ~ 25

Author(s):

K. Stewart ◽

S. Tragoudas

Keyword(s):

Interconnect Testing ◽

Networks On Chips

RF Front-end System Gain and Linearity Built-in Test

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.59 ◽

2006 ◽

Cited By ~ 32

Author(s):

Qi Wang ◽

M. Soma

Keyword(s):

Front End ◽

Rf Front End

Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.54 ◽

2006 ◽

Cited By ~ 1

Author(s):

Fang Liu ◽

P.K. Nikolov ◽

S. Ozev

Keyword(s):

Fault Diagnosis ◽

Analog Circuits ◽

Bayesian Framework ◽

Parametric Fault

Session Abstract

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.63 ◽

2006 ◽

Author(s):

P. Parvathala

An Overview of Failure Mechanisms in Embedded Flash Memories

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.19 ◽

2006 ◽

Cited By ~ 12

Author(s):

O. Ginez ◽

J.-M. Daga ◽

M. Combe ◽

P. Girard ◽

C. Landrault ◽

...

Keyword(s):

Failure Mechanisms ◽

Flash Memories ◽

Embedded Flash

On the Automation of the Test Flow of Complex SoCs

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.51 ◽

2006 ◽

Cited By ~ 13

Author(s):

D. Appello ◽

V. Tancorre ◽

P. Bernardi ◽

M. Grosso ◽

M. Rebaudengo ◽

...

Keyword(s):

Test Flow

Iterative OPDD Based Signal Probability Calculation

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.43 ◽

2006 ◽

Cited By ~ 1

Author(s):

A. Dutta ◽

N.A. Touba

Keyword(s):

Signal Probability ◽

Probability Calculation

Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.34 ◽

2006 ◽

Cited By ~ 5

Author(s):

Ruifeng Guo ◽

S. Mitra ◽

E. Amyeen ◽

Jinkyu Lee ◽

S. Sivaraj ◽

...

Improving Gate-Level ATPG by Traversing Concurrent EFSMs

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.39 ◽

2006 ◽

Cited By ~ 3

Author(s):

G. Di Guglielmo ◽

F. Fummi ◽

C. Marconcini ◽

G. Pravadelli

Scan Tests with Multiple Fault Activation Cycles for Delay Faults

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.91 ◽

2006 ◽

Cited By ~ 19

Author(s):

Zhuo Zhang ◽

S.M. Reddy ◽

I. Pomeranz ◽

Xijiang Lin ◽

J. Rajski

Keyword(s):

Delay Faults ◽

Multiple Fault ◽

Fault Activation