interconnect testing Latest Research Papers

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

IET Computers & Digital Techniques ◽

10.1049/cdt2.12028 ◽

2021 ◽

Author(s):

T. Nirmalraj ◽

S. Radhakrishnan ◽

S.K. Pandiyan

Keyword(s):

Automatic Diagnosis ◽

Interconnect Testing ◽

Single Fault

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2019.2962824 ◽

2020 ◽

Vol 67 (11) ◽

pp. 2657-2661 ◽

Cited By ~ 6

Author(s):

Tianming Ni ◽

Hao Chang ◽

Tai Song ◽

Qi Xu ◽

Zhengfeng Huang ◽

...

Keyword(s):

Interconnect Testing

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Integration ◽

10.1016/j.vlsi.2020.02.006 ◽

2020 ◽

Vol 72 ◽

pp. 171-182

Author(s):

Libao Deng ◽

Ning Sun ◽

Ning Fu

Keyword(s):

Boundary Scan ◽

Interconnect Testing ◽

Testing Design

Flexible hose interconnect testing for parabolic troughs with nitrate salt

10.1063/5.0029000 ◽

2020 ◽

Author(s):

Ryan Shininger ◽

Kyle Kattke ◽

Mark Anderson ◽

Francisco Ortiz Vives ◽

Mirko Saur ◽

...

Keyword(s):

Nitrate Salt ◽

Flexible Hose ◽

Interconnect Testing

Interconnect Testing for 2.5D ‐ and 3D‐SICs

Handbook of 3D Integration ◽

10.1002/9783527697052.ch10 ◽

2019 ◽

pp. 209-230

Author(s):

Shi‐Yu Huang

Keyword(s):

Interconnect Testing

Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs

2017 IEEE CPMT Symposium Japan (ICSJ) ◽

10.1109/icsj.2017.8240124 ◽

2017 ◽

Author(s):

Kouhei Ohtani ◽

Naho Osato ◽

Masaki Hashizume ◽

Hiroyuki Yotsuyanagi ◽

Shyue-Kung Lu

Keyword(s):

Interconnect Testing ◽

3D Ics ◽

Open Defects ◽

Resistive Open Defects

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2821506 ◽

2016 ◽

Vol 21 (2) ◽

pp. 1-23 ◽

Cited By ~ 12

Author(s):

Dong Xiang ◽

Kele Shen

Keyword(s):

Network On Chip ◽

Interconnect Testing ◽

Multicast Scheme ◽

On Chip

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

IEICE Transactions on Information and Systems ◽

10.1587/transinf.2015edp7273 ◽

2016 ◽

Vol E99.D (11) ◽

pp. 2723-2733

Author(s):

Widiant ◽

Masaki HASHIZUME ◽

Shohei SUENAGA ◽

Hiroyuki YOTSUYANAGI ◽

Akira ONO ◽

...

Keyword(s):

Interconnect Testing ◽

Test Circuit ◽

Open Defects

Embedded Memory Interface Logic and Interconnect Testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2014.2354381 ◽

2015 ◽

Vol 23 (9) ◽

pp. 1946-1950 ◽

Cited By ~ 2

Author(s):

Baker Mohammad

Keyword(s):

Embedded Memory ◽

Interconnect Testing ◽

Memory Interface

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

Journal of Electronic Testing ◽

10.1007/s10836-015-5515-7 ◽

2015 ◽

Vol 31 (2) ◽

pp. 207-215 ◽

Cited By ~ 9

Author(s):

Igor Gadelha Pereira ◽

Leonardo Alves Dias ◽

Cleonilson Protásio de Souza

Keyword(s):

Shift Register ◽

Interconnect Testing ◽

Global Interconnect

interconnect testing
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Flexible hose interconnect testing for parabolic troughs with nitrate salt

Interconnect Testing for 2.5D ‐ and 3D‐SICs

Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

Embedded Memory Interface Logic and Interconnect Testing

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

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interconnect testingRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Flexible hose interconnect testing for parabolic troughs with nitrate salt

Interconnect Testing for 2.5D ‐ and 3D‐SICs

Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

Embedded Memory Interface Logic and Interconnect Testing

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

interconnect testing
Recently Published Documents