This paper presents a new power converter topology<br>generated by the integration of the asymmetrical ZVS-PWM dcdc converter with a switched-capacitor ladder-type commutation<br>cell. Circuit operation and theoretical analysis with emphasis on<br>the soft-commutation process are included in the paper. The<br>main advantage of the proposed converter with respect to the<br>conventional asymmetrical half-bridge dc-dc converter is the<br>reduction of the voltage stress across the power switches to the<br>half of the input dc bus voltage, enabling the utilization of lower<br>voltage rating components. Experiments conducted on a<br>laboratory prototype with 1.4 kW power-rating, 800 V input<br>voltage, 48 V output voltage and 100 kHz switching frequency<br>are included, to verify the theoretical analysis and the design<br>methodology. The maximum efficiency of the experimental nonoptimized prototype was 93.6%.<br>Index Terms - Asymmetrical dc-dc converter, pulse-widthmodulation, switched-capacitor, zero voltage switching.<div><br><br></div>
Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS
