Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS
2017 ◽
Vol 52
(10)
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pp. 2563-2575
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2019 ◽
Vol 66
(1)
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pp. 16-20
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2019 ◽
Vol 66
(8)
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pp. 2876-2887
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2018 ◽
Vol 53
(9)
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pp. 2584-2594
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