Inter-Signal Timing Skew Compensation Of Source-Synchronized Parallel Links With Incremental Signaling

This thesis deals with inter-signal timing skew compensation of source-synchronized multi-Gbytes/s parallel links with both voltage-mode and current-mode incremental signaling schemes. To compensate for the inter-signal timing skew of parallel links with voltage-mode incremental signaling, an early/late block that detects the rising and falling edges of the pulses generated by inter-signal timing skews at the far end of the channels, and subsequently allocates the optimal sampling point of the sampler of each data bit to maximize the timing margins. Two cascaded delay-locked loops are employed to place the sampling clock to the optimal sampling position of each data bit. To compensate for the inter-signal timing skew of parallel links with current-mode incremental signaling, each current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values. The feedback at the front-end of the receiver minimizes the dependence of the input imedance of the receiver on the channel current so that data dependent impedance mismatch is minimized. Inter-signal timing skews are compensated by inserting a delay line in each channel.

Inter-Signal Timing Skew Compensation Of Source-Synchronized Parallel Links With Incremental Signaling

This thesis deals with inter-signal timing skew compensation of source-synchronized multi-Gbytes/s parallel links with both voltage-mode and current-mode incremental signaling schemes. To compensate for the inter-signal timing skew of parallel links with voltage-mode incremental signaling, an early/late block that detects the rising and falling edges of the pulses generated by inter-signal timing skews at the far end of the channels, and subsequently allocates the optimal sampling point of the sampler of each data bit to maximize the timing margins. Two cascaded delay-locked loops are employed to place the sampling clock to the optimal sampling position of each data bit. To compensate for the inter-signal timing skew of parallel links with current-mode incremental signaling, each current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values. The feedback at the front-end of the receiver minimizes the dependence of the input imedance of the receiver on the channel current so that data dependent impedance mismatch is minimized. Inter-signal timing skews are compensated by inserting a delay line in each channel.

INS/GNSS Integration with Account for Timing Skew and Displacement of GNSS Antenna. Experience of Practical Realization

We examine two aspects specific to complex data fusion algorithms in integrated strapdown inertial navigation systems aided by global positioning systems, with their inherent spatial separation between the GNSS antenna phase center and the inertial measurement unit, as well as with the timing skew between their measurements. The first aspect refers to modifications of mathematical models used in INS/GNSS integration. The second one relates to our experience in their application in onboard airborne navigation algorithms developed by Moscow Institute of Electromechanics and Automatics.