2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Latest Publications

TOTAL DOCUMENTS

267

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Published By IEEE

9781479909209, 9781479909186

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757412 ◽

2014 ◽

Cited By ~ 17

Author(s):

Fatih Hamzaoglu ◽

Umut Arslan ◽

Nabhendra Bisnik ◽

Swaroop Ghosh ◽

Manoj B. Lal ◽

...

Keyword(s):

Cmos Technology

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4.2 A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with 118mV droop and 230ns response time for a 5A/5ns load transient

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757346 ◽

2014 ◽

Cited By ~ 18

Author(s):

Min Kyu Song ◽

Joseph Sankman ◽

Dongsheng Ma

Keyword(s):

Response Time

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28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and <-100dBc reference spur for 802.11ac

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757518 ◽

2014 ◽

Cited By ~ 2

Author(s):

Yu-Li Hsueh ◽

Lan-Chou Cho ◽

Chih-Hsien Shen ◽

Yi-Chien Tsai ◽

Tzu-Chan Chueh ◽

...

Keyword(s):

Frequency Synthesizer ◽

Reference Spur

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9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757381 ◽

2014 ◽

Cited By ~ 6

Author(s):

Shuli Geng ◽

Dang Liu ◽

Yanfeng Li ◽

Huiying Zhuo ◽

Woogeun Rhee ◽

...

Keyword(s):

Enhancement Technique ◽

Link Margin

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13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757418 ◽

2014 ◽

Cited By ~ 7

Author(s):

Bharan Giridhar ◽

Nathaniel Pinckney ◽

Dennis Sylvester ◽

David Blaauw

Keyword(s):

Sense Amplifier

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Session 25 overview: High-bandwidth low-power DRAM and I/O: Memory subcommittee

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757571 ◽

2014 ◽

Author(s):

Uksong Kang ◽

James Sung

Keyword(s):

Low Power ◽

High Bandwidth

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3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757344 ◽

2014 ◽

Cited By ~ 4

Author(s):

Fujian Lin ◽

Pui-In Mak ◽

Rui Martins

Keyword(s):

Current Reuse ◽

Passive Mixers

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17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757436 ◽

2014 ◽

Cited By ~ 6

Author(s):

Haifeng Ma ◽

Ronan van der Zee ◽

Bram Nauta

Keyword(s):

Power Amplifier ◽

Frequency Regulation ◽

Switching Frequency ◽

Class D ◽

Optimal Efficiency

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21.2 A 2.3GHz fractional-N dividerless phase-locked loop with −112dBc/Hz in-band phase noise

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757470 ◽

2014 ◽

Cited By ~ 3

Author(s):

Po-Chun Huang ◽

Wei-Sung Chang ◽

Tai-Cheng Lee

Keyword(s):

Phase Noise ◽

Phase Locked Loop

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19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757456 ◽

2014 ◽

Cited By ~ 1

Author(s):

Konosuke Watanabe ◽

Kenichiro Yoshii ◽

Nobuhiro Kondo ◽

Kenichi Maeda ◽

Toshio Fujisawa ◽

...

Keyword(s):

Storage Device ◽

Flash Storage

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2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

4.2 A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with 118mV droop and 230ns response time for a 5A/5ns load transient

28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and <-100dBc reference spur for 802.11ac

9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications

13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS

Session 25 overview: High-bandwidth low-power DRAM and I/O: Memory subcommittee

3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF

17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation

21.2 A 2.3GHz fractional-N dividerless phase-locked loop with −112dBc/Hz in-band phase noise

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Latest Publications