2019 Symposium on VLSI Circuits
Latest Publications

TOTAL DOCUMENTS

140

(FIVE YEARS 0)

H-INDEX

6

(FIVE YEARS 0)

Published By IEEE

9784863487208

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

VLSI Circuits 2019 Short Course

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778188 ◽

2019 ◽

Keyword(s):

Vlsi Circuits ◽

Short Course

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A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778200 ◽

2019 ◽

Cited By ~ 1

Author(s):

Jing Li ◽

Zhao Chen ◽

Mingliang Tan ◽

Douwe van Willigen ◽

Chao Chen ◽

...

Keyword(s):

3D Ultrasound ◽

Element Level ◽

Ultrasound Probes

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A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778010 ◽

2019 ◽

Author(s):

Ji-Hwan Seol ◽

Dennis Sylvester ◽

David Blaauw ◽

Taekwang Jang

Keyword(s):

Phase Locked Loop ◽

Digital Phase ◽

Reference Spur

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Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778016 ◽

2019 ◽

Author(s):

T. Tanaka ◽

K. Tabuchi ◽

K. Tatehora ◽

Y. Shiiki ◽

S. Nakagawa ◽

...

Keyword(s):

Low Power ◽

Gas Molecules ◽

Ppm Level

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An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8777944 ◽

2019 ◽

Cited By ~ 1

Author(s):

Wei-Hsiang Huang ◽

Su-Hao Wu ◽

Zhi-Xin Chen ◽

Yun-Shiang Shu

Keyword(s):

Sar Adc ◽

Input Range ◽

Calibration Free

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A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778051 ◽

2019 ◽

Cited By ~ 2

Author(s):

Dirk Pfaff ◽

Shahaboddin Moazzeni ◽

Leisheng Gao ◽

Mei-Chen Chuang ◽

Xin-Jie Wang ◽

...

Keyword(s):

Fully Adaptive

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A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778093 ◽

2019 ◽

Cited By ~ 2

Author(s):

Harijot Singh Bindra ◽

Anne-Johan Annema ◽

Simon M. Louwsma ◽

Bram Nauta

Keyword(s):

Sar Adc ◽

Dynamic Bias

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A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778095 ◽

2019 ◽

Cited By ~ 10

Author(s):

Chandrakanth R. Chappidi ◽

Kaushik Sengupta

Keyword(s):

Power Amplifier

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A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778126 ◽

2019 ◽

Author(s):

Hyeonho Han ◽

Woojun Choi ◽

Youngcheol Chae

Keyword(s):

Impedance Monitoring

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A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2.

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778187 ◽

2019 ◽

Cited By ~ 1

Author(s):

Shunsuke Okumura ◽

Makoto Yabuuchi ◽

Kenichiro Hijioka ◽

Koichi Nose

Keyword(s):

Memory Architecture ◽

Many Core

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