A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines ◽

10.1109/fccm.2013.21 ◽

2013 ◽

Author(s):

Cheng Liu ◽

Colin Lin Yu ◽

Hayden Kwok-Hay So

Keyword(s):

Coarse Grained ◽

High Level Synthesis ◽

Reconfigurable Array ◽

Synthesis Methodology ◽

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High Level Synthesis Methodology for Exploring Loop Unrolling Factor and Functional Datapath

2018 International Conference on Advanced Computation and Telecommunication (ICACAT) ◽

10.1109/icacat.2018.8933661 ◽

2018 ◽

Author(s):

Pallabi Sarkar ◽

Mrinal Kanti Naskar ◽

Anirban Sengupta

Keyword(s):

High Level Synthesis ◽

Loop Unrolling ◽

Synthesis Methodology ◽

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A New High-Level Synthesis Methodology of Cascaded Continuous-Time$SigmaDelta$Modulators

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2006.875310 ◽

2006 ◽

Vol 53 (8) ◽

pp. 739-743 ◽

Author(s):

R. Tortosa ◽

J.M. De La Rosa ◽

F.V. Fernandez ◽

A. Rodriguez-Vazquez

Keyword(s):

Continuous Time ◽

High Level Synthesis ◽

Synthesis Methodology ◽

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An automated flow for the High Level Synthesis of coarse grained parallel applications

2013 International Conference on Field-Programmable Technology (FPT) ◽

10.1109/fpt.2013.6718370 ◽

2013 ◽

Author(s):

Vito Giovanni Castellana ◽

Fabrizio Ferrandi

Keyword(s):

Parallel Applications ◽

Coarse Grained ◽

High Level Synthesis ◽

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High level synthesis methodology from c to fpga used for a network protocol communication

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311103 ◽

2004 ◽

Author(s):

M. Diaby ◽

M. Tuna ◽

J.-L. Desbarbieux ◽

F. Wajsburt

Keyword(s):

Network Protocol ◽

High Level Synthesis ◽

Synthesis Methodology ◽

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High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

2010 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2010.8 ◽

2010 ◽

Author(s):

Sotirios Xydis ◽

Kiamal Pekmestzi ◽

Dimitrios Soudris ◽

George Economakos

Keyword(s):

Coarse Grained ◽

High Level Synthesis ◽

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A HIGH-LEVEL SYNTHESIS METHODOLOGY FOR DEDICATED DSP ARCHITECTURES

The International Conference on Electrical Engineering ◽

10.21608/iceeng.1999.62512 ◽

1999 ◽

Vol 2 (2) ◽

pp. 291-304

Author(s):

E. TALKHAN ◽

ALY SALAMA ◽

F. HASHIM

Keyword(s):

High Level Synthesis ◽

Synthesis Methodology ◽

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A New Efficient High-Level Synthesis Methodology for Lower Power Design

2009 International Conference on New Trends in Information and Service Science ◽

10.1109/niss.2009.20 ◽

2009 ◽

Author(s):

Chi-Ho Lin ◽

Dal-Hwan Yoon

Keyword(s):

High Level Synthesis ◽

Lower Power ◽

Synthesis Methodology ◽

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Our Parallelizing High-Level Synthesis Methodology

SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits ◽

10.1007/1-4020-7838-2_4 ◽

2006 ◽

pp. 51-57

Keyword(s):

High Level Synthesis ◽

Synthesis Methodology ◽

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Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815655 ◽

2008 ◽

Author(s):

Ganghee Lee ◽

Seokhyun Lee ◽

Kiyoung Choi

Keyword(s):

Reconfigurable Architecture ◽

Coarse Grained ◽

High Level Synthesis ◽

Synthesis Techniques ◽

Automatic Mapping ◽

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A high-level synthesis methodology for embedded mixed analog/digital processing systems

2003 46th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2003.1562577 ◽

2006 ◽

Author(s):

C. Alippi ◽

M. Stellini

Keyword(s):

Digital Processing ◽

High Level Synthesis ◽

Synthesis Methodology ◽

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