Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip

2006 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2006.311345 ◽

2006 ◽

Author(s):

Balasubramanian Sethuraman

Keyword(s):

Reconfigurable Networks ◽

Networks On Chip ◽

Power Efficient ◽

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C26. An Integrated Power-efficient Mapping and Routing Technique for Mesh-based Networks-on-Chip

2013 30th National Radio Science Conference (NRSC) ◽

10.1109/nrsc.2013.6587934 ◽

2013 ◽

Keyword(s):

Networks On Chip ◽

Power Efficient ◽

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Reconfigurable Networks-on-Chip

Integrated Optical Interconnect Architectures for Embedded Systems - Embedded Systems ◽

10.1007/978-1-4419-6193-8_7 ◽

2012 ◽

pp. 201-240 ◽

Author(s):

Wim Heirman ◽

Iñigo Artundo ◽

Christof Debaes

Keyword(s):

Reconfigurable Networks ◽

Networks On Chip ◽

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Reconfigurable Networks-on-Chip

10.1007/978-1-4419-9341-0 ◽

2012 ◽

Author(s):

Sao-Jie Chen ◽

Ying-Cherng Lan ◽

Wen-Chung Tsai ◽

Yu-Hen Hu

Keyword(s):

Reconfigurable Networks ◽

Networks On Chip ◽

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Multicasting based topology generation and core mapping for a power efficient networks-on-chip

Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 ◽

10.1145/1283780.1283868 ◽

2007 ◽

Author(s):

Balasubramanian Sethuraman ◽

Ranga Vemuri

Keyword(s):

Networks On Chip ◽

Power Efficient ◽

Topology Generation ◽

On Chip ◽

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Reconfigurable Networks on Chip: DRNoC architecture

Journal of Systems Architecture ◽

10.1016/j.sysarc.2010.04.003 ◽

2010 ◽

Vol 56 (7) ◽

pp. 293-302 ◽

Author(s):

Yana E. Krasteva ◽

Eduardo de la Torre ◽

Teresa Riesgo

Keyword(s):

Reconfigurable Networks ◽

Networks On Chip ◽

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Hardware accelerator for biological protein sequence alignment on reconfigurable Networks-on-Chip

2015 IEEE East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2015.7493125 ◽

2015 ◽

Author(s):

Mehdi Modarressi ◽

Faezeh Faghih ◽

Maryam Modarressi

Keyword(s):

Sequence Alignment ◽

Protein Sequence ◽

Hardware Accelerator ◽

Reconfigurable Networks ◽

Networks On Chip ◽

Protein Sequence Alignment ◽

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Power-efficient deterministic and adaptive routing in torus networks-on-chip

Microprocessors and Microsystems ◽

10.1016/j.micpro.2011.05.009 ◽

2012 ◽

Vol 36 (7) ◽

pp. 571-585 ◽

Author(s):

Dara Rahmati ◽

Hamid Sarbazi-Azad ◽

Shaahin Hessabi ◽

Abbas Eslami Kiasari

Keyword(s):

Adaptive Routing ◽

Networks On Chip ◽

Power Efficient ◽

On Chip ◽

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Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip

2006 International Symposium on System-on-Chip ◽

10.1109/issoc.2006.321979 ◽

2006 ◽

Author(s):

Pekka Rantala ◽

Teijo Lehtonen ◽

Jouni Isoaho ◽

Juha Plosila

Keyword(s):

Fault Tolerant ◽

Reconfigurable Networks ◽

Networks On Chip ◽

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Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

10.4995/thesis/10251/90419 ◽

2017 ◽

Author(s):

JOSÉ VICENTE ESCAMILLA LÓPEZ

Keyword(s):

Networks On Chip ◽

Power Efficient ◽

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A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

Microprocessors and Microsystems ◽

10.1016/j.micpro.2010.09.004 ◽

2011 ◽

Vol 35 (2) ◽

pp. 139-151 ◽

Author(s):

Chris Jackson ◽

Simon J. Hollis

Keyword(s):

Routing Algorithm ◽

Reconfigurable Networks ◽

Networks On Chip ◽

Dynamically Reconfigurable ◽

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