Single-pixel polarimetric direction of arrival estimation using programmable coding metasurface aperture

This paper presents a single-pixel polarimetric compressive sensing (CS)-based direction of arrival (DoA) estimation technique using a cavity backed programmable coding metasurface aperture. The single-pixel DoA retrieval technique relies on a dynamically modulated waveform diversity, enabling spatially incoherent radiation masks to encode the incoming plane waves on the radar aperture using a single channel. The polarimetric nature of the wave-chaotic coded metasurface ensures that the DOA estimation is sensitive to the polarization state of the incoming waves. We show that the polarimetric single-pixel DoA concept can be realized by encoding the polarization information of the incoming waves at the physical layer level within the antenna. A dynamically reconfigurable wave-chaotic metasurface, which possesses a structured sparsity of dual-polarized coded metamaterial elements, is proposed for the proof of concept. It is shown that by encoding and compressing the source generated far-field incident waves into a single channel, we can retrieve high fidelity polarimetric DoA information from compressed measurements.

Overlooked Ionic Phenomena Affecting the Electrical Conductivity of Liquid Crystals

Liquid crystal devices, such as displays, various tunable optical components, and sensors, are becoming increasingly ubiquitous. Basic physical properties of liquid crystal materials can be controlled by external physical fields, thus making liquid crystal devices dynamically reconfigurable. The tunability of liquid crystals offers exciting opportunities for the development of new applications, including advanced electronic and photonic devices, by merging the concepts of flat optics, tunable metasurfaces, nanoplasmonics, and soft matter biophotonics. As a rule, the tunability of liquid crystals is achieved by applying an electric field. This field reorients liquid crystals and changes their physical properties. Ions, typically present in liquid crystals in minute quantities, can alter the reorientation of liquid crystals through the well-known screening effect. Because the electrical conductivity of thermotropic liquid crystals is normally caused by ions, an understanding of ion generation processes in liquid crystals is of utmost importance to existing and emerging technologies relying on such materials. That is why measuring of electrical conductivity of liquid crystals is a standard part of their material characterization. Measuring the electrical conductivity of liquid crystals is a very delicate process. In this paper, we discuss overlooked ionic phenomena caused by interactions of ions with substrates of the liquid crystal cells. These interactions affect the measured values of the DC electrical conductivity of liquid crystals and make them dependent on the cell thickness.

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.