VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity
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2013 ◽
Vol 36
(2)
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pp. 52-59
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2005 ◽
Vol 41
(10)
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pp. 2983-2985
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2006 ◽
Vol 53
(4)
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pp. 892-904
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