An effective high-level synthesis approach for dynamically reconfigurable systems

2000 ◽  
Author(s):  
Xue-Jie Zhang ◽  
Kam-Wing Ng
Keyword(s):  
High Level Synthesis ◽  
Reconfigurable Systems ◽  
Dynamically Reconfigurable ◽  
High Level ◽  
Synthesis Approach

scholarly journals FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2024
Author(s):  
Julián Caba ◽  
Fernando Rincón ◽  
Jesús Barba ◽  
José Antonio de la Torre ◽  
Juan Carlos López
Keyword(s):  
Software Industry ◽  
Design Flow ◽  
High Level Synthesis ◽  
Reconfigurable Systems ◽  
Hardware Accelerators ◽  
Testing Environment ◽  
Development Life Cycle ◽  
Verification Process ◽  
Specialized Hardware ◽  
High Level

High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times.

Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach

2016 ◽  
Vol 24 (9) ◽  
pp. 2946-2959 ◽  
Author(s):  
Jeyavijayan JV Rajendran ◽  
Ozgur Sinanoglu ◽  
Ramesh Karri
Keyword(s):  
High Level Synthesis ◽  
High Level ◽  
Synthesis Approach
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