Low phase noise and low power CMOS LC voltage controlled oscillator for 5-GHz WLAN applications

2005 ◽  
Author(s):  
L. Bouzerara ◽  
M.T. Belaroussi ◽  
A. Slimane ◽  
M.B. Guermaz
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Voltage Controlled Oscillator ◽  
Low Power Cmos ◽  
5 Ghz ◽  
Low Phase Noise

Design of 5 GHz low-power CMOS LC VCO based on complementary cross-coupled topology with modified tail current-shaping technique

2014 ◽  
Vol 6 (6) ◽  
pp. 573-580 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Po-Hung Chen ◽  
Yao-Yen Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Measurement Results ◽  
Low Power Cmos ◽  
5 Ghz ◽  
Low Phase Noise ◽  
Manufacture Company

In this paper, a low-power CMOS LC voltage-controlled oscillator (VCO) with body-biasing and low-phase noise with Q-enhancement techniques is presented. A self-body biased circuit is introduced that can reduce power consumption. Some derivations of the Q-enhancement and how to improve the phase noise of the circuit are also discussed. This chip is implemented by the Taiwan Semiconductor Manufacture Company 0.18 µm 1P6M process. The measurement results exhibit a tuning range of 14.7% from 4.92 to 5.7 GHz at a supply voltage of 1.4 V. The power consumption of the core circuit and figure of merit are 2.5 mW and −188.6 dBc/Hz. The phase noise is −118 dBc/Hz@1 MHz at an operation frequency of 4.94 GHz.

Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 1010-1013
Author(s):  
Tsung Han Han ◽  
Meng Ting Hsu ◽  
Cheng Chuan Chung
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Voltage Controlled Oscillators ◽  
Communication Circuits ◽  
5 Ghz ◽  
Low Phase Noise

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control

2018 ◽  
Vol 27 (05) ◽  
pp. 1850072
Author(s):  
Chenggang Yan ◽  
Chen Hu
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Feedback Loop ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Amplitude Control ◽  
Ultra Low Power ◽  
Class C ◽  
Low Phase Noise ◽  
Near Threshold

A 400[Formula: see text][Formula: see text]W near-threshold supply class-C voltage controlled oscillator (VCO) with amplitude feedback loop and auto amplitude control (AAC) is proposed in this paper. The amplitude feedback loop and AAC ensure the robust startup of the proposed VCO and automatically adapts it to the class-C mode in steady state. Consequently, ultra-low power can be achieved in AAC mode and low phase noise, high swing can be achieved in AAC off mode. The proposed VCO with AAC gets ultra-low power consumption by limiting the oscillating amplitude and driving the proposed VCO into the deep Class-C mode. Additionally, the peak value detector is employed in this work to boost the controlling voltage of capacitors bank. Thus, a low on resistance of switch transistors is obtained, which increases the Q value of capacitors bank. The simulated phase noise is [Formula: see text]124.5[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset with the 1.16[Formula: see text]GHz oscillation frequency. In this case, the figure-of-merit including tuning range (FOMT) of proposed VCO is [Formula: see text]195[Formula: see text]dBc/Hz. The proposed VCO is fabricated in SMIC 40[Formula: see text]nm CMOS process and consumes 0.62[Formula: see text]mA from 0.65[Formula: see text]V supply. The measured phase noise is [Formula: see text]109[Formula: see text]dBc/Hz and FOMT is [Formula: see text]179[Formula: see text]dBc/Hz.

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