The $24\times 24$ Reversible Vedic Multiplier

Mapping Intimacies ◽

10.1109/mysurucon52639.2021.9641598 ◽

2021 ◽

Author(s):

Krishnaveni D ◽

Supriya K ◽

Suhas H R ◽

Varshini N ◽

Sushma R ◽

...

Keyword(s):

Vedic Multiplier

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An Efficient QCA Vedic Multiplier for Nanotechnology Applications

2021 International Conference on Intelligent Technologies (CONIT) ◽

10.1109/conit51480.2021.9498464 ◽

2021 ◽

Author(s):

Divya Tripathi ◽

Subodh Wairya

Keyword(s):

Vedic Multiplier

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Design of area and delay efficient Vedic multiplier using Carry Select Adder

2015 International Conference on Information Processing (ICIP) ◽

10.1109/infop.2015.7489396 ◽

2015 ◽

Author(s):

G. R. Gokhale ◽

S. R. Gokhale

Keyword(s):

Vedic Multiplier ◽

Carry Select Adder

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FPGA implementation of high speed Vedic multiplier

International Conference & Workshop on Electronics & Telecommunication Engineering (ICWET 2016) ◽

10.1049/cp.2016.1144 ◽

2016 ◽

Author(s):

S.N. Gadakh ◽

A.S. Khade

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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Applications of vedic multiplier designs - A review

2015 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions) ◽

10.1109/icrito.2015.7359309 ◽

2015 ◽

Author(s):

Akanksha Kant ◽

Shobha Sharma

Keyword(s):

Vedic Multiplier

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High Speed Sixty Four Bit Vedic Multiplier

10.1109/cict53865.2020.9672441 ◽

2021 ◽

Author(s):

Yaswanth Sai ◽

M.P.R. Prasad

Keyword(s):

Vedic Multiplier

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Implementation of 9 bit Signed Vedic Multiplier on Zed Board

2018 Second International Conference on Electronics, Communication and Aerospace Technology (ICECA) ◽

10.1109/iceca.2018.8474583 ◽

2018 ◽

Author(s):

Soumya Kapur ◽

Nidhi Gaur ◽

Garima Vyas ◽

Anu Mehra

Keyword(s):

Vedic Multiplier

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Performance Evaluation of Vedic Multiplier Using Multiplexer-Based Adders

Lecture Notes in Electrical Engineering - Microelectronics, Electromagnetics and Telecommunications ◽

10.1007/978-981-13-1906-8_36 ◽

2018 ◽

pp. 349-356 ◽

Author(s):

N. Udaya Kumar ◽

K. Bala Sindhuri ◽

U. Subbalakshmi ◽

P. Kiranmayi

Keyword(s):

Performance Evaluation ◽

Vedic Multiplier

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Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique

Circuits and Systems ◽

10.4236/cs.2016.79224 ◽

2016 ◽

Vol 07 (09) ◽

pp. 2593-2602 ◽

Author(s):

S. K. Manikandan ◽

C. Palanisamy

Keyword(s):

Reduction Technique ◽

Vedic Mathematics ◽

Vedic Multiplier

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Reduction of Partial Products for Vedic Multiplier

International Journal of Engineering Research and ◽

10.17577/ijertv4is040065 ◽

2015 ◽

Vol V4 (04) ◽

Author(s):

Sunil Patel ◽

Deepak Parashar ◽

Keyword(s):

Vedic Multiplier

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FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter

2013 International Conference on Energy Efficient Technologies for Sustainability ◽

10.1109/iceets.2013.6533349 ◽

2013 ◽

Author(s):

U. C. S. P. Kumar ◽

A. S. Goud ◽

A. Radhika

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier ◽

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