Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique

Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

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Design and Implementation of Reversible Vedic Multiplier with Trlic

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.f7862.038620 ◽

2020 ◽

Vol 8 (6) ◽

pp. 1530-1534

Keyword(s):

Embedded System ◽

Power Dissipation ◽

High Speed ◽

Mathematical Problem ◽

Processing Application ◽

Vedic Mathematics ◽

Programmable Filter ◽

Vedic Multiplier ◽

Rules And Principles ◽

Fixed Input

The 'Vedic Mathematics' is the name given to the ancient system of mathematics with a unique technique of calculations based on simple rules and principles with which any mathematical problem can be solved with the help of arithmetic, algebra, geometry or trigonometry. In any of the fastest ALU, multiplier play an inevitable role. There is always a demand on high speed multiplier due to the raising limitation on delay. Increasing the speed of a multiplier there are number of new techniques have been implemented in which multiplier using Vedic mathematics are foremost one. The system performance and delay depend on the performance of multiplier used in it. Multiplier are used in different area such as cryptography, image processing application, embedded system application, programmable filter application etc .One of the major techniques to scale back the power dissipation is Reversible logic. There is no loss of data therefore power dissipation is reduced producing distinctive output for fixed input and vice-versa. The main objective of the project is to scale back the TRLIC of the multiplier factor by exploitation of Vedic arithmetic.The proposed methods are designed using VHDL Programming language, simulation and synthesis are done using Cadence RTL compiler in 180nm technology.

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Vedic Multiplier Implementation for High Speed Factorial Computation

International Journal of New Practices in Management and Engineering ◽

10.17762/ijnpme.v1i04.8 ◽

2012 ◽

Vol 1 (04) ◽

pp. 01-06

Author(s):

Prof. Sharayu Waghmare

Keyword(s):

Comparative Analysis ◽

High Speed ◽

Vlsi Architecture ◽

Path Delay ◽

Vedic Mathematics ◽

Vedic Multiplier ◽

The Given ◽

Mathematical Operations ◽

Indian Mathematics

Vedic Mathematics arise from the prehistoric classification of Indian mathematics that was recreated by Tirthaji. Ancient mathematical operations are depending on sixteen methods. In this article, a new VLSI architecture to compute factorial of the given number with Vedic based multiplier is proposed. Simulations are performed using Xilinx ISE 14.2. Effective comparative analysis is made with existing multipliers to prove the momentous development in competence and high speed operation. This efficient multiplier is implemented in the proposed factorial architecture which significantly reduces the path delay and provides better optimization.

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FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics.

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0255157 ◽

2013 ◽

Vol 2 (5) ◽

pp. 51-57 ◽

Cited By ~ 6

Author(s):

Keyword(s):

Low Power ◽

High Speed ◽

Fpga Implementation ◽

Vedic Mathematics ◽

Vedic Multiplier

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DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS

Journal of Circuits System and Computers ◽

10.1142/s0218126614500923 ◽

2014 ◽

Vol 23 (07) ◽

pp. 1450092 ◽

Cited By ~ 1

Author(s):

PRABIR SAHA ◽

DEEPAK KUMAR ◽

PARTHA BHATTACHARYYA ◽

ANUP DANDAPAT

Keyword(s):

Power Consumption ◽

High Speed ◽

Cmos Technology ◽

Propagation Delay ◽

Boolean Logic ◽

Dynamic Power ◽

Vedic Mathematics ◽

Vedic Multiplier ◽

Layout Area ◽

And Performance

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

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