High Level Synthesis of Parallel Tile Processing Units with non-uniform memory accesses

2008 NORCHIP ◽  
2008 ◽  
Author(s):  
R. Corvino ◽  
S. Mancini ◽  
R. Guizzetti
Keyword(s):  
High Level Synthesis ◽  
Memory Accesses ◽  
High Level

FPGA Memory Optimization in High-Level Synthesis

2020 ◽  
pp. 51-81
Author(s):  
Mingjie Lin ◽  
Juan Escobedo
Keyword(s):  
Data Reuse ◽  
High Level Synthesis ◽  
Reconfigurable Architectures ◽  
Relative Distance ◽  
Memory Optimization ◽  
Performance Improvements ◽  
Memory Subsystem ◽  
Significant Performance ◽  
Memory Accesses ◽  
High Level

High-level synthesis (HLS) with FPGA can achieve significant performance improvements through effective memory partitioning and meticulous data reuse. In this chapter, the authors will first explore techniques that have been adopted directly from systems that possess a fixed memory subsystem such as CPUs and GPUs (Section 2). Section 3 will focus on techniques that have been developed specifically for reconfigurable architectures which generate custom memory subsystems to take advantage of the peculiarities of a family of affine code called stencil code. The authors will focus on techniques that exploit memory banking to allow for parallel, conflict-free memory accesses in Section 3.1 and techniques that generate an optimal memory micro-architecture for data reuse in Section 3.2. Finally, Section 4 will explore the technique handling code still belonging to the affine family but the relative distance between the addresses.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level

Exact and Practical Modulo Scheduling for High-Level Synthesis

2019 ◽  
Vol 12 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Julian Oppermann ◽  
Melanie Reuter-Oppermann ◽  
Lukas Sommer ◽  
Andreas Koch ◽  
Oliver Sinnen
Keyword(s):  
High Level Synthesis ◽  
Modulo Scheduling ◽  
High Level
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