A design methodology to implement memory accesses in high-level synthesis

2011 ◽  
Author(s):  
Christian Pilato ◽  
Fabrizio Ferrandi ◽  
Donatella Sciuto
Keyword(s):  
Design Methodology ◽  
High Level Synthesis ◽  
Memory Accesses ◽  
High Level

Design Methodology for High-Level Synthesis

1992 ◽  
pp. 297-335 ◽  
Author(s):  
Daniel D. Gajski ◽  
Nikil D. Dutt ◽  
Allen C-H Wu ◽  
Steve Y-L Lin
Keyword(s):  
Design Methodology ◽  
High Level Synthesis ◽  
High Level

scholarly journals IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance

2014 ◽  
Vol 2014 ◽  
pp. 1-17
Author(s):  
Sharad Sinha ◽  
Thambipillai Srikanthan
Keyword(s):  
Design Methodology ◽  
Arithmetic Functions ◽  
High Level Synthesis ◽  
Mathematical Functions ◽  
Chip Design ◽  
Design Complexity ◽  
Application Characteristics ◽  
Ip Cores ◽  
Program Recognition ◽  
High Level

Intellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity. C/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity. In the work presented here, we present a design methodology that combines these two individual methodologies and is therefore more powerful. We discuss our proposed methodology in the context of supporting efficient hardware synthesis of a class of mathematical functions without altering original C/C++ source code. Additionally, we also discuss and propose methods to integrate legacy IP cores in existing HLS flows. Relying on concepts from the domains of program recognition and optimized low level implementations of such arithmetic functions, the described design methodology is a step towards intelligent synthesis where application characteristics are matched with specific architectural resources and relevant IP cores in a transparent manner for improved area-delay results. The combined methodology is more aware of the target hardware architecture than the conventional HLS flow. Implementation results of certain compute kernels from a commercial tool Vivado-HLS as well as proposed flow are also compared to show that proposed flow gives better results.

FPGA Memory Optimization in High-Level Synthesis

2020 ◽  
pp. 51-81
Author(s):  
Mingjie Lin ◽  
Juan Escobedo
Keyword(s):  
Data Reuse ◽  
High Level Synthesis ◽  
Reconfigurable Architectures ◽  
Relative Distance ◽  
Memory Optimization ◽  
Performance Improvements ◽  
Memory Subsystem ◽  
Significant Performance ◽  
Memory Accesses ◽  
High Level

High-level synthesis (HLS) with FPGA can achieve significant performance improvements through effective memory partitioning and meticulous data reuse. In this chapter, the authors will first explore techniques that have been adopted directly from systems that possess a fixed memory subsystem such as CPUs and GPUs (Section 2). Section 3 will focus on techniques that have been developed specifically for reconfigurable architectures which generate custom memory subsystems to take advantage of the peculiarities of a family of affine code called stencil code. The authors will focus on techniques that exploit memory banking to allow for parallel, conflict-free memory accesses in Section 3.1 and techniques that generate an optimal memory micro-architecture for data reuse in Section 3.2. Finally, Section 4 will explore the technique handling code still belonging to the affine family but the relative distance between the addresses.

scholarly journals Layout Modeling and Design Space Exploration in Pss1 System

VLSI Design ◽  
1997 ◽  
Vol 5 (2) ◽  
pp. 211-221
Author(s):  
Fur-Shing Tsai ◽  
Yu-Chin Hsu
Keyword(s):  
Design Methodology ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
Design Parameters ◽  
Information Feedback ◽  
Synthesis System ◽  
Hardware Costs ◽  
High Level

This paper presents the design methodology used in PSS1, a high level synthesis system designed for computation dominated applications. It includes a behavior synthesizer and an area optimizer. Based on a pre-defined architecture, the behavior synthesizer translates a description into a number of designs with different delays and hardware costs. Based on a two-level layout model, the area optimizer fine-tunes the physical design using the information feedback from the layout tools. All the tools are linked by an X-window interface in which users can traverse among different tools and interactively change the design parameters. The output is linked to Lager system [7], a silicon assembler. The layout model allows a designer to interactively merge/split modules, change the shape of modules, and define the pin positions of modules. Experiments show that a considerable area improvement has been achieved using this methodology.

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