2016 26th International Conference on Field Programmable Logic and Applications (FPL)
Latest Publications

TOTAL DOCUMENTS

102

(FIVE YEARS 0)

H-INDEX

9

(FIVE YEARS 0)

Published By IEEE

9782839918442

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Towards a hardware-assisted information flow tracking ecosystem for ARM processors

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577396 ◽

2016 ◽

Author(s):

Muhammad Abdul Wahab ◽

Pascal Cotret ◽

Mounir Nasr Allah ◽

Guillaume Hiet ◽

Vianney Lapotre ◽

...

Keyword(s):

Information Flow ◽

Information Flow Tracking

Download Full-text

Conference proceedings FPL 2016

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577298 ◽

2016 ◽

Keyword(s):

Conference Proceedings

Download Full-text

FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577339 ◽

2016 ◽

Author(s):

Dimitris Agiakatsikas ◽

Ediz Cetin ◽

Oliver Diessel

Keyword(s):

Error Recovery ◽

Memory Error ◽

Recovery Scheme ◽

Hybrid Configuration

Download Full-text

Stress-aware routing to mitigate aging effects in SRAM-based FPGAs

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577341 ◽

2016 ◽

Author(s):

Behnam Khaleghi ◽

Behzad Omidi ◽

Hussam Amrouch ◽

Jorg Henkel ◽

Hossein Asadi

Keyword(s):

Download Full-text

Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577369 ◽

2016 ◽

Author(s):

Pietro Fezzardi ◽

Fabrizio Ferrandi

Keyword(s):

High Level Synthesis ◽

Bug Detection ◽

Memory Accesses ◽

Download Full-text

Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577361 ◽

2016 ◽

Author(s):

Sidharth Maheshwari ◽

Gourav Modi ◽

Siddhartha ◽

Nachiket Kapre

Keyword(s):

Sparse Matrix ◽

Fpga Acceleration

Download Full-text

Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577352 ◽

2016 ◽

Author(s):

Paul Grigoras ◽

Pavel Burovskiy ◽

Wayne Luk ◽

Spencer Sherwin

Keyword(s):

Large Scale ◽

Sparse Matrix ◽

Matrix Vector Multiplication ◽

Download Full-text

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577334 ◽

2016 ◽

Author(s):

Malte Vesper ◽

Dirk Koch ◽

Kizheppatt Vipin ◽

Suhaib A. Fahmy

Keyword(s):

Open Source ◽

High Performance ◽

Download Full-text

Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreams

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577347 ◽

2016 ◽

Author(s):

Ismail San ◽

Nicole Fern ◽

Cetin Kaya Koc ◽

Kwang-Ting Cheng

Keyword(s):

Instruction Sequences

Download Full-text

Modelling delay degradation due to NBTI in FPGA Look-up tables

2016 26th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2016.7577328 ◽

2016 ◽

Author(s):

Mohammad Naouss ◽

Francois Marc

Download Full-text