Owing to the failure of Dennard’s scaling, the past decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are
Posit
and RISC-V.
Posit
was introduced in mid-2017 as a viable alternative to IEEE-754, and RISC-V provides a commercial-grade open source Instruction Set Architecture (ISA). In this article, we bring these two technologies together and propose a Configurable
Posit
Enabled RISC-V Core called PERI.
The article provides insights on how the Single-Precision Floating Point (“F”) extension of RISC-V can be leveraged to support
posit
arithmetic. We also present the implementation details of a parameterized and feature-complete
posit
Floating Point Unit (FPU). The configurability and the parameterization features of this unit generate optimal hardware, which caters to the accuracy and energy/area tradeoffs imposed by the applications, a feature not possible with IEEE-754 implementation. The
posit
FPU has been integrated with the RISC-V compliant SHAKTI C-class core as an execution unit. To further leverage the potential of
posit
, we enhance our
posit
FPU to support two different exponent sizes (with posit-size being 32-bits), thereby enabling multiple-precision at runtime. To enable the compilation and execution of C programs on PERI, we have made minimal modifications to the GNU C Compiler (GCC), targeting the “F” extension of the RISC-V. We compare
posit
with IEEE-754 in terms of hardware area, application accuracy, and runtime. We also present an alternate methodology of integrating the
posit
FPU with the RISC-V core as an accelerator using the custom opcode space of RISC-V.
PERI
