Fast Key-Value Lookups with Node Tracker

Lookup operations for in-memory databases are heavily memory bound, because they often rely on pointer-chasing linked data structure traversals. They also have many branches that are hard-to-predict due to random key lookups. In this study, we show that although cache misses are the primary bottleneck for these applications, without a method for eliminating the branch mispredictions only a small fraction of the performance benefit is achieved through prefetching alone. We propose the Node Tracker (NT), a novel programmable prefetcher/pre-execution unit that is highly effective in exploiting inter key-lookup parallelism to improve single-thread performance. We extend NT with branch outcome streaming (BOS) to reduce branch mispredictions and show that this achieves an extra 3× speedup. Finally, we evaluate the NT as a pre-execution unit and demonstrate that we can further improve the performance in both single- and multi-threaded execution modes. Our results show that, on average, NT improves single-thread performance by 4.1× when used as a prefetcher; 11.9× as a prefetcher with BOS; 14.9× as a pre-execution unit and 18.8× as a pre-execution unit with BOS. Finally, with 24 cores of the latter version, we achieve a speedup of 203× and 11× over the single-core and 24-core baselines, respectively.

PERI

Owing to the failure of Dennard’s scaling, the past decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE-754, and RISC-V provides a commercial-grade open source Instruction Set Architecture (ISA). In this article, we bring these two technologies together and propose a Configurable Posit Enabled RISC-V Core called PERI. The article provides insights on how the Single-Precision Floating Point (“F”) extension of RISC-V can be leveraged to support posit arithmetic. We also present the implementation details of a parameterized and feature-complete posit Floating Point Unit (FPU). The configurability and the parameterization features of this unit generate optimal hardware, which caters to the accuracy and energy/area tradeoffs imposed by the applications, a feature not possible with IEEE-754 implementation. The posit FPU has been integrated with the RISC-V compliant SHAKTI C-class core as an execution unit. To further leverage the potential of posit , we enhance our posit FPU to support two different exponent sizes (with posit-size being 32-bits), thereby enabling multiple-precision at runtime. To enable the compilation and execution of C programs on PERI, we have made minimal modifications to the GNU C Compiler (GCC), targeting the “F” extension of the RISC-V. We compare posit with IEEE-754 in terms of hardware area, application accuracy, and runtime. We also present an alternate methodology of integrating the posit FPU with the RISC-V core as an accelerator using the custom opcode space of RISC-V.

Development and Performance Analysis of Pneumatic Soft-Bodied Bionic Basic Execution Unit

This paper studies the design of pneumatic soft-bodied bionic basic execution unit with soft-rigid combination, which can be used as an actuator for pneumatic soft-bodied robots and soft-bodied manipulators. This study is inspired by structural characteristics and motion mechanism of biological muscles, combined with the nonlinear hyperelasticity of silica gel and the insertion of thin leaf spring structure in the nonretractable layer. Response surface analysis and numerical simulation algorithm are used to determine the optimal combination of structural dimension parameters by taking the maximum output bending angle of the basic executing unit as the optimization objective. Based on Odgen’s third-order constitutive model, the deformation analysis model of the basic execution unit is established. The physical model of pneumatic soft-bodied bionic basic execution unit is prepared through 3D printing, shape deposition, soft lithography, and other processing methods. Finally, the motion and dynamic characteristics of the physical model are tested through experiments and result analysis, thus obtaining curves and empirical formulas describing the motion and dynamic characteristics of the basic execution unit. The relevant errors are compared with the deformation analysis model of the execution unit to verify the feasibility and effectiveness of the design of the pneumatic soft-bodied bionic basic execution unit. The above research methods, research process, and results can provide a reference for the research and implementation of pneumatic and hydraulic driven soft-bodied robots and grasping actuators of soft-bodied manipulators.

Development of designing and implementation method of magnetic execution unit of downhole valve for the bottomhole assembly

The structure of two types of magnetic valve is offered and the calculation methods of their pull-in force developed as well. The formulas of calculation of pull-in force in the main area of valves’ power characteristics are obtained. Experimental data are in alignment with theoretical calculations. Power characteristics of offered structures of magnetic valves may be changed in terms of the offered structural execution of magnetic valves. Experimental test of obtained formulas has been carried out. The ways of changing the power characteristics of magnetic valves in accordance with the requirements of certain applications are presented. The structures of magnetic reversing valves for drilling tools used in well drilling in various oil-gas bearing areas of SOCAR have been developed.

Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages

Many processors have evolved in the past century; Out of which, Reduced Instruction set Computing (RISC) processors are well known for their ease of use. The next in line was the Microprocessor without Interlocked pipelining stages (MIPS) RISC based architecture. Less number of instructions, good amount of registers makes these processors a boon to use. Often times, MIPS processors loose the battle against their contenders due to lack of speed. Hence, there is a sheer necessity in designing a more robust system that has all the advantages of MIPS. Over time, there have been designs that could solve the power drawbacks and the area optimizations. However, performance criterion is mostly neglected. This paper emphasizes on the performance metric of pipelined 32-bit MIPS microprocessor. This processor supports RISC architecture and has been designed under Harvard architecture. Pipelining technique is used to solve the problem of low performance and achieve smaller execution times. The processor has four pipes. Pipes are the structures which store data. Pipes can be viewed as register banks. These pipes are generally used to store the intermediate data. The design contains various modules like ALU, Instruction fetch register, Execution unit, Memory, Program counter (PC). Verilog HDL has been used to implement the design. The software used is Xilinx ISE for design and ISIM simulator has been used for simulation purposes. The applications of this MIPS microprocessor are abundant. MIPS microprocessor can be used to carry out the fundamental tasks and an application specific core/IP/processor can be designed and combined with MIPS. This facilitates in meeting the goals of high performance, lower time-to-market and cost- effectiveness. Some application specific uses can be for music systems, PDA, Image processing etc.

ADDITIVE-SUBTRACTIVE TECHNOLOGIES – EFFECTIVE TRANSITION TO INNOVATION PRODUCTION

At present a rapid development of additive technologies for the growth of metal and alloy products takes place. Each additive technology has its own rational field of application and its own characteristic set of advantages and disadvantages. The most promising technologies are new 3DMP-technologies of wire sedimentation/welding deposition by a method electric arc welding in combination with subtractive machining technologies (additive-subtractive technologies). The application of 3DMP-technologies in comparison with common and some powder technologies results in the considerable decrease of production costs and substantial increase of growth productivity, for them it is characteristic a high coefficient of initial material beneficial use. The advantage in use of additive-subtractive technologies (AST) consists in a possibility of the alternative use of additive and subtractive transitions at the formation of a part within the limits of one technological operation in a full compliance with the principle of community and constancy of technological bases. But AST peculiarity requires a complex solution of interrelated engineering and scientific problems including those in the field of design of products, material machining, engineering procedure automation and CAD systems. For instance, in consequence of that the realization of 3DMP-technology is possible only under conditions of complete process automation, in the presence of a subtractive module having 3-5 controlled coordinates, for the equipment on the whole the NC system is necessary which controls the execution unit displacement along six coordinate axes and more.

Proposed Regulations for Enforcement of the Purports of Binding Banking Documents in Rastin Banking

To facilitate and accelerate the enforcement of binding banking documents and distribute the enforcement burden of the registration offices of the State Organization for Registration of Deeds and Properties, courts, and judicial authorities, a new mechanism for “enforcement of the purports of binding banking documents in Rastin Banking” was designed. This mechanism can lead to positive and essential effects toward creating public trust in financial obligations and increasing the speed of collecting demands, in order to remove the problems resulting from enforcement of the purports of binding documents. In this paper, the proposed regulations are presented in two drafts of “The Bill for Enforcement of the Purports of Binding Banking documents in Rastin Banking” and “The Bylaw for Enforcement of the Purports of Binding Banking Documents and Handling Complaints against Executive Operations in Rastin Banking”.The newly designed method has been compiled considering all financial, legal, and executive issues. In the proposed regulations, a part of the executive path for enforcement of the purports of binding banking documents is transferred from the “Document Registration Unit” into a newly established unit called the “Bank Documents Execution Unit” (BDEU), located in every bank, and this new unit will follow the enforcement of the purports of binding banking documents, instead of the “Document Registration Unit”. All the legal necessities, the necessary cooperation with the judicial authorities, and the necessary procedures for hearing and settlement have all been designed to not let any spoiling of the rights of the parties, while also working efficiently.This procedure is a model that can be adapted for other countries, especially those countries that have a large number of legal disputes and the process of dispute settlement is very lengthy and cumbersome. Since the Administration of Justice is the main factor to promote all the other social and economic circumstances, the proposed model can prepare a way to improve the social and economic well-being.