During labor ECG Monitoring is one of the most used method to determine the condition of the fetus. The type of monitoring varies from patients to patients. Few require continuous monitoring because of medication while others require only intermittent monitoring. The fetal ECG is the only information source in early stage diagnosis of fetal health and status. This paper describes the implementation of a system based on FPGA which denoises the abdominal ECG and separates the Fetal ECG from the abdominal signal. For preprocessing a VLSI hardware in FPGA for wavelet transform method is designed and implemented. The embedded architecture on FPGA is based on quadrature spline wavelet transform. FPGA implementation of quadrature spline wavelet transform filter was done with different multipliers. The extraction of fetal electrocardiogram signal was done using slope threshold and two stage template search method where the fetal ECG is extracted from the abdominal ECG. The logical elements, power and delay for the proposed architecture is reported in this paper. For implementation Cyclone II kit and Quartus software was used. In future the classification method will be implemented.