Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2019.2912920 ◽

2020 ◽

Vol 39 (6) ◽

pp. 1328-1339 ◽

Author(s):

Kyle Kuan ◽

Tosiron Adegbija

Keyword(s):

Energy Efficient ◽

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Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2843940 ◽

2017 ◽

Vol 22 (4) ◽

pp. 1-20 ◽

Author(s):

Kaige Yan ◽

Lu Peng ◽

Mingsong Chen ◽

Xin Fu

Keyword(s):

Energy Efficient ◽

Mobile Platforms ◽

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A Locality-Aware, Energy-Efficient Cache Design for Large-Scale Multi-Core Systems

2018 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData) ◽

10.1109/cybermatics_2018.2018.00107 ◽

2018 ◽

Author(s):

Abdulrahman Alshegaifi ◽

Chun-Hsi Huang

Keyword(s):

Energy Efficient ◽

Large Scale ◽

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An energy efficient cache design using spin torque transfer (STT) RAM

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design - ISLPED '10 ◽

10.1145/1840845.1840931 ◽

2010 ◽

Author(s):

Mitchelle Rasquinha ◽

Dhruv Choudhary ◽

Subho Chatterjee ◽

Saibal Mukhopadhyay ◽

Sudhakar Yalamanchili

Keyword(s):

Energy Efficient ◽

Spin Torque ◽

Spin Torque Transfer ◽

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PS-cache: an energy-efficient cache design for chip multiprocessors

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2013.6618832 ◽

2013 ◽

Author(s):

Youngjoon Jo ◽

Michael Goldfarb ◽

Milind Kulkarni

Keyword(s):

Energy Efficient ◽

Chip Multiprocessors ◽

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A CASE STUDY OF ENERGY-EFFICIENT LOOP INSTRUCTION CACHE DESIGN FOR EMBEDDED MULTITASKING SYSTEMS

Proceedings of the 1st International Conference on Smart Grids and Green IT Systems ◽

10.5220/0003951001970202 ◽

2012 ◽

Keyword(s):

Energy Efficient ◽

Instruction Cache ◽

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TCache: An energy-efficient DRAM cache design

2017 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2017.8050698 ◽

2017 ◽

Author(s):

Jiacong He ◽

Joseph Callenes-Sloan

Keyword(s):

Energy Efficient ◽

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Energy-efficient cache design using variable-strength error-correcting codes

Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11 ◽

10.1145/2000064.2000118 ◽

2011 ◽

Author(s):

Alaa R. Alameldeen ◽

Ilya Wagner ◽

Zeshan Chishti ◽

Wei Wu ◽

Chris Wilkerson ◽

...

Keyword(s):

Energy Efficient ◽

Error Correcting Codes ◽

Variable Strength ◽

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Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

Journal of Computer Science and Technology ◽

10.1007/s11390-011-1150-7 ◽

2011 ◽

Vol 26 (3) ◽

pp. 504-519 ◽

Author(s):

An-Guo Ma ◽

Yu Cheng ◽

Zuo-Cheng Xing

Keyword(s):

Energy Efficient ◽

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Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.23919/date48585.2020.9116212 ◽

2020 ◽

Author(s):

Chen Jie ◽

Igor Loi ◽

Luca Benini ◽

Davide Rossi

Keyword(s):

Low Power ◽

Energy Efficient ◽

Ultra Low Power ◽

Instruction Cache ◽

Core Cluster ◽

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An Energy Efficient Cache Design for Multi-core Processors

2013 IEEE International Conference on Green Computing and Communications and IEEE Internet of Things and IEEE Cyber, Physical and Social Computing ◽

10.1109/greencom-ithings-cpscom.2013.243 ◽

2013 ◽

Author(s):

Cao Xiangrong ◽

Zhang Xiaolin

Keyword(s):

Energy Efficient ◽

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