Modeling cache performance for embedded systems

This paper presents a cache performance model for embedded systems. The need for efficient cache design in embedded systems has led to the exploration of various methods of design for optimal cache configurations for embedded processor. Better users’ experiences are realized by improving performance parameters of embedded systems. This work presents a cache hit rate estimation model for embedded systems that can be used to explore optimal cache configurations using Bourneli’s binomial cumulative probability based on application of reuse distance profiles. The model presented was evaluated using three mibench benchmarks which are bitcount, basicmath and FFT for 4kb, 8kb, 16kb, 32kb and 64kb sizes of cache under 2-way, 4-ways, 8-ways and 16-ways set associative configurations, all using least recently-used (LRU) replacement policy. The results were compared with the results obtained using sim-cheetah from simplescalar simulators suite. The mean errors for bitcount, basicmath, and FFT benchmarks are 0.0263%, 2.4476%, and 1.9000% respectively. Therefore, the mean error for the three benchmarks is equal to 1.4579%. The margin of errors in the results was below 5% and within the acceptable limits showing that the model can be used to estimate hit rates of cache and to explore cache design options.

Understanding Cache Compression

Hardware cache compression derives from software-compression research; yet, its implementation is not a straightforward translation, since it must abide by multiple restrictions to comply with area, power, and latency constraints. This study sheds light on the challenges of adopting compression in cache design—from the shrinking of the data until its physical placement. The goal of this article is not to summarize proposals but to put in evidence the solutions they employ to handle those challenges. An in-depth description of the main characteristics of multiple methods is provided, as well as criteria that can be used as a basis for the assessment of such schemes. It is expected that this article will ease the understanding of decisions to be taken for the design of compressed systems and provide directions for future work.

Comparative Analysis of Spintronic Memories for Low Power on-chip Caches

The continuous downscaling in CMOS devices has increased leakage power and limited the performance to a few GHz. The research goal has diverted from operating at high frequencies to deliver higher performance in essence with lower power. CMOS based on-chip memories consumes significant fraction of power in modern processors. This paper aims to explore the suitability of beyond CMOS, emerging magnetic memories for the use in memory hierarchy, attributing to their remarkable features like nonvolatility, high-density, ultra-low leakage and scalability. NVSim, a circuit-level tool, is used to explore different design layouts and memory organizations and then estimate the energy, area and latency performance numbers. A detailed system-level performance analysis of STT-MRAM and SOT-MRAM technologies and comparison with 22[Formula: see text]nm SRAM technology are presented. Analysis infers that in comparison to the existing 22[Formula: see text]nm SRAM technology, SOT-MRAM is more efficient in area for memory size [Formula: see text][Formula: see text]KB, speed and energy consumption for cache size [Formula: see text][Formula: see text]KB. A typical 256[Formula: see text]KB SOT-MRAM cache design is 27.74% area efficient, 2.97 times faster and consumes 76.05% lesser leakage than SRAM counterpart and these numbers improve for larger cache sizes. The article deduces that SOT-MRAM technology has a promising potential to replace SRAM in lower levels of computer memory hierarchy.