A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations

2021 ◽  
Vol 68 (1) ◽  
pp. 471-475
Author(s):  
Junran Pu ◽  
Wang Ling Goh ◽  
Vishnu P. Nambiar ◽  
Anh Tuan Do
Keyword(s):  
Neural Network ◽  
Low Power ◽  
Routing Algorithm ◽  
Spiking Neural Network ◽  
Low Area ◽  
Hardware Implementations ◽  
Neural Network Hardware ◽  
Congestion Aware

scholarly journals An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations

2018 ◽  
Vol 48 (3) ◽  
pp. 1777-1788 ◽  
Author(s):  
Yuling Luo ◽  
Lei Wan ◽  
Junxiu Liu ◽  
Jim Harkin ◽  
Yi Cao
Keyword(s):  
Neural Network ◽  
Low Cost ◽  
Spiking Neural Network ◽  
Hardware Implementations ◽  
Neural Network Hardware

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations

2013 ◽  
Vol 24 (12) ◽  
pp. 2451-2461 ◽  
Author(s):  
Snaider Carrillo ◽  
Jim Harkin ◽  
Liam J. McDaid ◽  
Fearghal Morgan ◽  
Sandeep Pande ◽  
...  
Keyword(s):  
Neural Network ◽  
Network On Chip ◽  
Spiking Neural Network ◽  
Hierarchical Network ◽  
Hardware Implementations ◽  
Neural Network Hardware ◽  
On Chip

scholarly journals A modular T-mode design approach for analog neural network hardware implementations

1992 ◽  
Vol 27 (5) ◽  
pp. 701-713 ◽  
Author(s):  
B. Linares-Barranco ◽  
E. Sanchez-Sinencio ◽  
A. Rodriguez-Vazquez ◽  
J.L. Huertas
Keyword(s):  
Neural Network ◽  
Design Approach ◽  
Mode Design ◽  
Hardware Implementations ◽  
Neural Network Hardware ◽  
Analog Neural Network
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